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HS-565ARH 데이터시트 PDF




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부품번호 HS-565ARH 기능
기능 Radiation Hardened High Speed/ Monolithic Digital-to-Analog Converter
제조업체 Intersil Corporation
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HS-565ARH 데이터시트, 핀배열, 회로
Semiconductor
HS-565ARH
March 1996
Radiation Hardened High Speed,
Monolithic Digital-to-Analog Converter
Features
Description
• Devices QML Qualified in Accordance with
MIL-PRF-38535
• Detailed Electrical and Screening Requirements
are Contained in SMD# 5962-96755 and Harris’ QM
Plan
• DAC and Reference on a Single Chip
• Pin Compatible with AD-565A and HI-565A
• Very High Speed: Settles to 0.50 LSB in 500ns Max
• Monotonicity Guaranteed Over Temperature
• 0.50 LSB Max Nonlinearity Guaranteed Over
Temperature
• Low Gain Drift (Max., DAC Plus Reference) 50ppm/oC
The HS-565ARH is a fast, radiation hardened 12-bit current out-
put, digital-to-analog converter. The monolithic chip includes a
precision voltage reference, thin-film R-2R ladder, reference
control amplifier and twelve high-speed bipolar current
switches.
The Harris Semiconductor Dielectric Isolation process provides
latch-up free operation while minimizing stray capacitance and
leakage currents, to produce an excellent combination of speed
and accuracy. Also, ground currents are minimized to produce a
low and constant current through the ground terminal, which
reduces error due to code-dependent ground currents.
HS-565ARH die are laser trimmed for a maximum integral nonlin-
earity error of ±0.25 LSB at +25oC. In addition, the low noise bur-
ied zener reference is trimmed both for absolute value and mini-
mum temperature coefficient.
• Total Dose Hardness to 100K RAD
±0.75 LSB Accuracy Guaranteed Over Temperature
(±0.125 LSB Typical at +25oC)
Applications
• High Speed A/D Converters
• Precision Instrumentation
• Signal Reconstruction
Functional Diagram
REF OUT VCC
43
+
-
REF 6 19.95K
IN
REF 5
GND
10V
IREF
0.5mA
3.5K
+
-
3K
BIP.
OFF.
8
9.95K
DAC
IO
(4X IREF
X CODE)
11 20V
SPAN
5K
10 10V
SPAN
5K
9
OUT
2.5K
7 12
-VEE PWR 24 . . . 13
GND MSB LSB
Ordering Information
PART NUMBER
5962R9675501VJC
5962R9675501VXC
HS1-565ARH (SAMPLE)
HS9-565ARH (SAMPLE)
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
SCREENING LEVEL
MIL-PRF-38535 Level V
MIL-PRF-38535 Level V
Sample
Sample
PACKAGE
24 Lead SBDIP
24 Lead Ceramic Flatpack
24 Lead SBDIP
24 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996
1
Spec Number 518795
File Number 3278.2




HS-565ARH pdf, 반도체, 판매, 대치품
Specifications HS-565ARH
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETERS
SYMBOL
CONDITIONS
GROUP A
LIMITS
SUB-
GROUP TEMPERATURE MIN TYP MAX UNITS
Output Offset
Unipolar
Bipolar
VOS
BPOE
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V
Figure 3, R2 = 50Fixed
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V,
R3 and R4 = 50Fixed
Figure 4
1, 2, 3 -55oC to +125oC
-
1, 2, 3 -55oC to +125oC
-
±0.01 ±0.05 % of
F.S.
±0.05 ±0.15 % of
F.S.
Power Supply Gain
Sensitivity
VCC
VEE
+PSS Note 3
-PSS Note 3
1, 2, 3
1, 2, 3
-55oC to +125oC
-55oC to +125oC
-
-
3 10 ppm of
F.S./%
15 25 ppm of
F.S./%
Temperature
Coefficients
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
External Adjustments
Gain Error
Bipolar Zero Error
AE
BPAE
BPZE
With Internal Reference
With Internal Reference
With Internal Reference
Fixed 50Resistor for R2
Figures 3
Fixed 50Resistor for R3 and
R4, Figure 4
Fixed 50Resistor for R3 and
R4, Figure 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-
-
-
-
-
-
1
5
10
±0.10
±0.10
±0.05
2
20
50
±0.25
±0.25
±0.10
ppm/oC
ppm/oC
ppm/oC
% of
F.S.
% of
F.S.
% of
F.S.
NOTES:
1. All voltages referenced to VSSD = VSSA = 0V
2. Unless otherwise specified VCC = +15V and VEE = -15V.
3. The Power Supply Gain Sensitivity is tested in reference to a VCC = +15V and VEE = -15V.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank. See AC Specifications in Table 3
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERS
Output Capacitance
Output Compliance
Voltage
Programmable Output
Ranges
SYMBOL
CONDITIONS
COUT f = 1MHz
Gain Adjustment Range
Figures 3, 4
NOTES
1, 2
1
1
1
1
1
1
1
TEMPERATURE MIN TYP MAX
+25oC
- 20 -
-55oC to +125oC -1.5
-
10
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
0
-2.5
0
-5
-10
±0.25
-
-
-
-
-
-
5
2.5
10
5
10
-
Bipolar Zero
Adjustment Range
Reference Input
Impedance
Output Resistance
Figure 4
RREF
ROUT
VSSD = VSSA = 0V, -15
VCC = +15V, VEE = -15V
VSSD = VSSA = 0V,
VCC = +15V, VEE = -15V,
Exclusive of Span Resistors
1
1
1
-55oC to +125oC ±0.15 -
-
-55oC to +125oC 15K 20K 25K
-55oC to +125oC 1.8K 2.5K 3.2K
UNITS
pF
V
V
V
V
V
V
% of
F.S.
% of
F.S.
Spec Number 518795
4

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HS-565ARH 전자부품, 판매, 대치품
HS-565ARH
respective change in temperature. The specification given is
the larger of the two, representing worst case drift.
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in gain
and offset of the D/A converter resulting from a change in -15V
or +15V supplies. It is specified under DC conditions and
expressed as parts per million of full scale range per percent of
change in power supply (ppm of FSR/%).
Compliance
Compliance Voltage is the maximum output voltage range
that can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only and
makes no claims to accuracy.
No Trim Operation
The HS-565ARH will perform as specified without calibration
adjustments. To operate without calibration, substitute 50
resistors for the 100trimming potentiometers: In Figure 3
replace R2 with 50; also remove the network on pin 8 and
connect 50to ground. For bipolar operation in Figure 4,
replace R3 and R4 with 50resistors.
With these changes, performance is guaranteed as shown
under Specifications, “External Adjustments”. Typical
unipolar zero will be ±0.50 LSB plus the op amp offset.
The feedback capacitor C must be selected to minimize
settling time.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half scale or the major
carry code transition from 011 . . . 1 to 100 . . . 0 or vice
versa. For example, if turn ON is greater than turn OFF for
011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0
exists, such that, the output momentarily glitches toward
zero output. Matched switching times and fast switching will
reduce glitches considerably.
Applying the HS-565ARH
OP AMP Selection
The HS-565ARH’s current output may be converted to
voltage using the standard connections shown in Figures 3
and 4. The choice of operational amplifier should be
reviewed for each application, since a significant trade-off
may be made between speed and accuracy. Remember
settling time for the DAC-amplifier combination is
(tD)2 + (tA)2
where tD, tA are settling times for the DAC and amplifier.
R2
100
REF OUT
VCC
43
BIP.
OFF.
8
+
-
6
REF
IN
REF 5
GND
19.95
K
HS-565ARH
10V
5K
IREF
0.5mA
9.95K
DAC
5K
3.5K
3K
+
-
IO
(4 x IREF
x CODE) 2.5K
100k
100
+15V
R1
50k
-15V
11
20V SPAN
10
10V SPAN VO
DAC
OUT
9
-C
+
R (SEE
TABLE 7)
CODE
INPUT
7
-VEE
24 . . . . . 13
MSB LSB
PWR
GND
R4
100
REF OUT
VCC
43
R3
100
BIP.
OFF.
8
+
-
6 19.95K
REF
IN
5
REF
GND
HS-565ARH
10V
5K
IREF
0.5mA
9.95K
DAC
5K
3.5K
3K
+
-
IO
(4 x IREF
x CODE) 2.5K
CODE
INPUT
11
20V SPAN
10
10V SPAN VO
DAC
OUT
9
-C
+
R (SEE
TABLE 7)
7
-VEE
24 . . . . . 13
MSB LSB
PWR
GND
FIGURE 4. BIPOLAR VOLTAGE OUTPUT
Calibration
Calibration provides the maximum accuracy from a
converter by adjusting its gain and offset errors to zero, For
the HS-565ARH, these adjustments are similar whether the
current output is used, or whether an external op amp is
added to convert this current to a voltage. Refer to Table 7
for the voltage output case, along with Figure 3 or 4.
Calibration is a two step process for each of the five output
ranges shown in Table 7. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translates the output characteristic, i.e. affects each code by
the same amount.
Next adjust positive FS. This is a gain error adjustment,
which rotates the output characteristic about the negative FS
value.
For the bipolar ranges, this approach leaves an error at the
zero code, whose maximum values is the same as for
integral nonlinearity error. In general, only two values of
output may be calibrated exactly; all others must tolerate
some error. Choosing the extreme end points (plus and
minus full scale) minimizes this distributed error for all other
codes.
FIGURE 3. UNIPOLAR VOLTAGE OUTPUT
Spec Number 518795
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