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HS-6664RH 데이터시트 PDF




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부품번호 HS-6664RH 기능
기능 Radiation Hardened 8K x 8 CMOS PROM
제조업체 Intersil Corporation
로고 Intersil Corporation 로고


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HS-6664RH 데이터시트, 핀배열, 회로
HS-6664RH
September 1995
Radiation Hardened
8K x 8 CMOS PROM
Features
Pinouts
• 1.2 Micron Radiation Hardened Bulk CMOS
• Total Dose 3 x 105 RAD (Si)
• Transient Output Upset >5 x 108 RAD (Si)/s
• LET >100 MEV-cm2/mg
• Fast Access Time - 35ns (Typical)
• Single 5V Power Supply
• Single Pulse 10V Field Programmable
• Synchronous Operation
• On-Chip Address Latches
• Three-State Outputs
• NiCr Fuses
• Low Standby Current <500µA (Pre-Rad)
• Low Operating Current <15mA/MHz
• Military Temperature Range -55oC to +125oC
28 LEAD CERAMIC SBDIP
CASE OUTLINE D28.6 MIL-STD-1835, CDIP2-T28
TOP VIEW
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ0 11
DQ1 12
DQ2 13
GND 14
28 VDD
27 P
26 NC
25 A8
24 A9
23 A11
22 G
21 A10
20 E
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
Description
The Intersil HS-6664RH is a radiation hardened 64K
CMOS PROM, organized in an 8K word by 8-bit for-
mat. The chip is manufactured using a radiation
hardened CMOS process, and utilizes synchronous
circuit design techniques to achieve high speed
performance with very low power dissipation.
On-chip address latches are provided, allowing easy
interfacing with microprocessors that use a
multiplexed address/data bus structure. The output
enable control (G) simplifies system interfacing by
allowing output data bus control in addition to the chip
enable control (E). All bits are manufactured storing a
logical “0” and can be selectively programmed for a
logical “1” at any bit location.
Applications for the HS-6664RH CMOS PROM
include low power microprocessor based instrumenta-
tion and communications systems, remote data acqui-
sition and processing systems, and processor control
storage.
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
28 LEAD FLATPACK
CASE OUTLINE K28.A MIL-STD-1835, CDFP3-F28
TOP VIEW
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VDD
P
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
† P must be hardwired at all times to VDD, except during programming.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
840
Spec Number 518741
File Number 3197.3




HS-6664RH pdf, 반도체, 판매, 대치품
Specifications HS-6664RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Guaranteed and 100% Tested.
PARAMETER
SYMBOL
(NOTES 1, 2, 3)
CONDITIONS
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
MIN MAX UNITS
Chip Enable Low Width
Chip Enable High Width
Read Cycle Time
TELEH
TEHEL
TELEL
VDD = 4.5V and 5.5V
VDD = 4.5V and 5.5V
VDD = 4.5V and 5.5V
9, 10, 11
9, 10, 11
9, 10, 11
-55oC TA +125oC
-55oC TA +125oC
-55oC TA +125oC
60
20
80
-
-
-
ns
ns
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume transition time 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1 TTL equivalent
load and CL 50pF.
3. All tests performed with P hardwired to VDD.
4. Address Access Time (TAVQV) = TELQV + TAVEL = 65ns (maximum).
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS, AC AND DC
PARAMETER
SYMBOL
(NOTE 2)
CONDITIONS
NOTES
TEMPERATURE
LIMITS
MIN MAX
UNITS
Input Capacitance
I/O Capacitance
Chip Enable Time
Output Enable Time
Chip Disable Time
Output Disable Time
CIN
CI/O
TELQX
TGLQX
TEHQZ
TGHQZ
VDD = Open, f = 1MHz
VDD = Open, f = 1MHz
VDD = 4.5V and 5.5V
VDD = 4.5V and 5.5V
VDD = 4.5V and 5.5V
VDD = 4.5V and 5.5V
1, 3 TA = +25oC
1, 3 TA = +25oC
3 -55oC TA +125oC
3 -55oC TA +125oC
3 -55oC TA +125oC
3 -55oC TA +125oC
-
-
5
5
-
-
15 pF
12 pF
- ns
- ns
15 ns
15 ns
NOTES:
1. All measurements referenced to device GND.
2. All tests performed with P hardwired to VDD.
3. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after design or process changes which would affect these characteristics.
TABLE 4. POST 100K RAD AC AND DC ELECTRICAL PERFORMANCE CHARACTERISTICS
NOTE: All AC and DC parameters are tested at the +25oC pre-irradiation limits.
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC)
PARAMETER
Standby Supply Current
Input Leakage Current
Output Low Voltage
Output High Voltage
SYMBOL
IDDSB
IOZ
II
VOL
VOH
DELTA LIMITS
±50µA
±1µA
±100nA
±60mV
±400mV
Spec Number 518741
843

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HS-6664RH 전자부품, 판매, 대치품
HS-6664RH
Intersil - Space Level (-Q) Product Flow (Note 1)
SEM - Traceable to Diffusion Method 2018
Wafer Lot Acceptance Method 5007
Internal Visual Inspection Method 2010, Condition A
Gamma Radiation Assurance Tests Method 1019
Nondestructive Bond Pull Method 2023
Customer Pre-Cap Visual Inspection (Note 2)
Temperature Cycling Method 1010, Condition C
Constant Acceleration Method 2001, Condition E Min, Y1
Particle Impact Noise Detection Method 2020, Condition A
Electrical Tests (Intersil’ Option)
Serialization
X-Ray Inspection Method 2012
Electrical Tests - Subgroup 1; Read and Record (T0)
Static Burn-In Method 1015, Condition B, 72 Hrs, +125oC Min.
Interim 1 Electrical Tests - Subgroup 1; Read and Record (T1)
Burn-In Delta Calculation (T0 -T1)
PDA Calculation 3% Subgroup 7
5% Subgroups 1, 7,
Dynamic Burn-In Method 1015, Condition D, 240 Hrs, +125oC
(Note 3)
Interim 2 Electrical Tests - Subgroup 1; Read and Record (T2)
Alternate Group A - Subgroups 1, 7, 9; Method 5005; Para
3.5.1.1
Burn-In Delta Calculation (T0 - T2)
PDA Calculation 3% Subgroup 7
5% Subgroups 1, 7,
Electrical Tests - Subgroup 3; Read and Record
Alternate Group A - Subgroups 3, 8B, 11; Method 5005; Para
3.5.1.1
Marking
Electrical Tests - Subgroup 2; Read and Record
Alternate Group A - Subgroups 2, 8A, 10; Method 5005;
Para 3.5.1.1
Gross Leak Tests Method 1014, 100%
Fine Leak Tests Method 1014, 100%
Customer Source Inspection (Note 2)
Group B Inspection Method 5005 (Note 2)
End-Point Electrical Parameters: B-5 - Subgroups 1, 2, 3,
7, 8A, 8B, 9, 10, 11; B-6 - Subgroups 1, 7, 9
Group D Inspection Method 5005 (Notes 2, 4)
End-Point Electrical Parameters: Subgroups 1, 7, 9
External Visual Inspection Method 2009
Data Package Generation (Note 4)
NOTES:
1. The notes of Method 5004, Table 1 shall apply; Unless Otherwise Specified.
2. These steps are optional, and should be listed on the individual purchase order(s), when required.
3. Intersil reserves the right of performing burn-in time temperature regression as defined by Table 1 of Method 1015.
4. Data package contains:
Assembly Attributes (post seal)
Test Attributes (includes Group A)
Shippable Serial Number List
Radiation Testing Certificate of Conformance
Wafer Lot Acceptance Report (Including SEM Report)
X-Ray Report and Film
Test Variables Data
Intersil -8 Product Flow
Internal Visual Inspection Method 2010 Condition B
Alternate
Gamma Radiation Assurance Tests Method 1019
Customer Pre-Cap Visual Inspection (Note 1)
Temperature Cycling Method 1010, Condition C
Fine and Gross Leak Tests Method 1014
Constant Acceleration Method 2001 Y1 30KG
Initial Electrical Tests
Dynamic Burn-In Method 1015, Condition D, 160 Hrs, +125oC
+25oC Electrical Tests - Subgroups 1, 7, 9
PDA Calculation 5% Subgroups 1, 7
Electrical Tests +125oC, -55oC
Group A Inspection Method 5005. 5% PDA (Note 3)
Brand
Customer Source Inspection (Note 1)
Group B Inspection Method 5005 (Notes 1, 2)
Group C Inspection Method 5005 (Notes 1, 2)
Group D Inspection Method 5005 (Notes 1, 2)
External Visual Inspection Method 2009
Data Package Generation (Note 4)
NOTES:
1. These steps are optional, and must be negotiated as part of order.
2. Group B, C and D data package contains Attributes Data.
3. Intersil reserves the right to perform Alternate Group A. The 5% PDA is still applicable.
4. ‘-8’ Data package contains:
Assembly Attributes (post seal)
Test Attributes (includes Group A)
Radiation Testing Certificate of Conformance
Certificate of Conformance (as found on shipper)
Spec Number 518741
846

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