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HS-80C85RH 데이터시트 PDF




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부품번호 HS-80C85RH 기능
기능 Radiation Hardened 8-Bit CMOS Microprocessor
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HS-80C85RH 데이터시트, 핀배열, 회로
HS-80C85RH
February 1996
Radiation Hardened
8-Bit CMOS Microprocessor
Features
• Devices QML Qualified in Accordance With
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95824 and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 105 RAD(Si)
- Transient Upset > 1 x 108 RAD(Si)/s
- Latch-up Free > 1 x 1012 RAD(Si)/s
• Low Standby Current 500µA Max
• Low Operating Current 5.0mA/MHz (X1 Input)
• Electrically Equivalent to Sandia SA 3000
• 100% Software Compatible with INTEL 8085
• Operation from DC to 2MHz, Post Radiation
• Single 5 Volt Power Supply
• On-Chip Clock Generator and System Controller
• Four Vectored Interrupt Inputs
• Completely Static Design
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55oC to +125oC
Description
The HS-80C85RH is an 8-bit CMOS microprocessor fabri-
cated using the Intersil radiation hardened self-aligned junc-
tion isolated (SAJI) silicon gate technology. Latch-up free
operation is achieved by the use of epitaxial starting material
to eliminate the parasitic SCR effect seen in conventional
bulk CMOS devices.
The HS-80C85RH is a functional logic emulation of the
HMOS 8085 and its instruction set is 100% software com-
patible with the HMOS device. The HS80C85RH is designed
for operation with a single 5 volt power supply. Its high level
of integration allows the construction of a radiation hardened
microcomputer system with as few as three ICs (HS-
80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/
56RH RAM I/O.
Pinouts
40 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835, CDIP2-T40
TOP VIEW
X1 1
X2 2
RESET OUT 3
SOD 4
SID 5
TRAP 6
RST 7.5 7
RST 6.5 8
RST 5.5 9
INTR 10
INTA 11
AD0 12
AD1 13
AD2 14
AD3 15
AD4 16
AD5 17
AD6 18
AD7 19
GND 20
40 VDD
39 HOLD
38 HLDA
37 CLOCK OUT
36 RESET IN
35 READY
34 IO / M
33 S1
32 RD
31 WR
30 ALE
29 S0
28 A15
27 A14
26 A13
25 A12
24 A11
23 A10
22 A9
21 A8
42 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
INTERSIL OUTLINE K42.A
TOP VIEW
X1
X2
RESET
OUT
SOD
SID
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
INTA
AD0
AD1
AD2
AD3
AD4
NC
NC
AD5
AD6
AD7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 VDD
41 HOLD
40 HLDA
39 CLOCK
OUT
38 RESET
37
IN
READY
36 IO / M
35 S1
34 RD
33 WR
32 ALE
31 S0
30 A15
29 A14
28 A13
27 A12
26 A11
25 A10
24 A9
23 A8
22 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518054
File Number 3036.2




HS-80C85RH pdf, 반도체, 판매, 대치품
HS-80C85RH
Pin Description (Continued)
SYMBOL
PIN
NUMBER TYPE
DESCRIPTION
INTR
10 I Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to
the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a
RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR
is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is
accepted.
INTA
11 O Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruc-
tion cycle after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some
other interrupt port.
RST 5.5
RST 6.5
RST 7.5
9
8
7
I Restart Interrupts: These three inputs have the same timing as INTR except they cause an
internal RESTART to be automatically inserted.
The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher
priority than INTR. In addition, they may be individually masked out using the SIM instruction.
TRAP
6 I Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as
INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority
of any interrupt. (See Table 6.)
RESET IN
36
I Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.
The data and address buses and the control lines are 3-stated during RESET and because of
the asynchronous nature of RESET the processor’s internal registers and flags may be altered
by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connec-
tion to an R-C network for power-on RESET delay (see Figure 1). Upon power-up, RESET IN
must remain low for at least 10 “clock cycle” after minimum VDD has been reached. For proper
reset operation after the power-up duration, RESET IN should be kept low a minimum of three
clock periods. The CPU is held in the reset condition as long as RESET IN is applied.
RESET OUT
3
O Reset Out: Reset Out indicates cpu is being reset. Can be used as a system reset. The signal
is synchronized to the processor clock and lasts an integral number of clock periods.
X1 1 I X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator.
X2 2 O X, can also be an external clock Input from a logic gate. The input frequency is divided by 2 to
give the processor’s internal operating frequency.
CLK 37 O Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input
period.
SID 5 I Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM
instruction is executed.
SOD
4 O Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction.
VCC
40 I Power: +5V supply.
GND
20 I Ground: Reference.
VDD
RESET IN
R1 C1
TYPICAL POWER-ON RESET RC VALUES
R1 = 75K
C1 = 1µF
Values may have to vary due to applied power supply ramp up time.
FIGURE 1. POWER-ON RESET CIRCUIT
4
Spec Number 518054

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HS-80C85RH 전자부품, 판매, 대치품
Specifications HS-80C85RH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
Input Capacitance
CIN VDD = Open, f = 1MHz
I/O Capacitance
CI/O
VDD = Open, f = 1MHz
Output Capacitance
COUT VDD = Open, f = 1MHz
NOTE:
1. All measurements referenced to device ground.
TEMPERATURE
TA = +25oC
TA = +25oC
TA = +25oC
LIMITS
MIN MAX
- 12
- 13
- 12
UNITS
pF
pF
pF
TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS
NOTE: The post irradiation test conditions and limits are the same as those listed in Tables 1 and 2.
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC; In Accordance With SMD)
TABLE 6. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY
NAME
PRIORITY
ADDRESS BRANCHED TO (1)
WHEN INTERRUPT OCCURS
TYPE TRIGGER
TRAP
1 24H Rising edge and high level until sampled.
RST 7.5
2
3CH
Rising edge (latched)
RST 6.5
3
34CH
High level until sampled.
RST 5.5
4
2CH
High level until sampled.
INTR
5
See Note 2
High level until sampled.
NOTES:
1. The processor pushes the PC on the stack before branching to the indicated address.
2. The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged.
SYMBOL
tAL
tLA
tLL
tLCK
tLC
tAD
tRD
tRAE
tCA
tDW
tWD
TABLE 7. BUS TIMING SPECIFICATION AS A tCYC DEPENDENT
HS-8OC85RH
SYMBOL
HS-8OC85RH
(1/2)T- 175
Minimum
tCC (3/2 + N)T - 175
(1/2)T- 175
Minimum
tCL (1/2)T - 190
(1/2)T-50
Minimum
tARY
(3/2)T - 500
(1/2)T- 125
Minimum
tHACK
(1/2)T - 160
(1/2)T- 100
Minimum
tHABF
(1/2)T +125
(5/2 + N)T - 375
Maximum
tHABE
(1/2)T +125
(3/2 + N)T - 375
Maximum
tAC (2/2)T - 200
(1/2)T- 130
Minimum
t1 (1/2)T-210
(1/2)T - 100
Minimum
t2 (1/2)T- 150
(3/2 + N)T - 175
Minimum
tRV (3/2)T - 200
(1/2)T-100
Minimum
tLDR
(4/2)T - 325
NOTE: N is equal to the total WAIT states T = tCYC
Minimum
Minimum
Maximum
Minimum
Maximum
Maximum
Minimum
Minimum
Minimum
Minimum
Maximum
Spec Number 518054
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관련 데이터시트

부품번호상세설명 및 기능제조사
HS-80C85RH

Radiation Hardened 8-Bit CMOS Microprocessor

Intersil Corporation
Intersil Corporation

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