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HS-82C37ARH 데이터시트 PDF




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부품번호 HS-82C37ARH 기능
기능 Radiation Hardened CMOS High Performance Programmable DMA Controller
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HS-82C37ARH 데이터시트, 핀배열, 회로
HS-82C37ARH
August 1995
Radiation Hardened CMOS High
Performance Programmable DMA Controller
Features
Description
• Radiation Hardened
- Total Dose >105 RAD (Si)
- Transient Upset > 108 RAD (Si)/s
- Latch Up Free EPI-CMOS
• Low Power Consumption
- IDDSB = 50µA Maximum
- IDDOP = 4.0mA/MHz Maximum
• Pin Compatible with NMOS 8237A and the Intersil
82C37A
The Intersil HS-82C37ARH is an enhanced, radiation
hardened CMOS version of the industry standard 8237A
Direct Memory Access (DMA) controller, fabricated using the
Intersil hardened field, self-aligned silicon gate CMOS
process. The HS-82C37ARH offers increased functionality,
improved performance, and dramatically reduced power
consumption for the radiation environment. The high speed,
radiation hardness, and industry standard configuration of
the HS-82C37ARH make it compatible with radiation
hardened microprocessors such as the HS-80C85RH and
the HS-80C86RH.
• High Speed Data Transfers Up To 2.5 MBPS With 5MHz
Clock
• Four Independent Maskable Channels With Autoinitializa-
tion Capability
• Expandable to Any Number of Channels
• Memory-to-Memory Transfer Capability
• CMOS Compatible
• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process
• Single 5V Supply
• Military Temperature Range -55oC to +125oC
The HS-82C37ARH can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization
feature. DMA requests may be generated by either
hardware or software, and each channel is independently
programmable with a variety of features for flexible
operation.
Static CMOS circuit design insures low operating power and
allows gated clock operation for an even further reduction of
power. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
The Intersil hardened field CMOS process results in
performance equal to or greater than existing radiation resis-
tant products at a fraction of the power.
Ordering Information
PART NUMBER
HS1-82C37ARH-Q
HS1-82C37ARH-8
HS1-82C37ARH-Sample
HS9-82C37ARH-Q
HS9-82C37ARH-8
HS9-82C37ARH/Sample
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
-55oC to +125oC
-55oC to +125oC
+25oC
PACKAGE
40 Lead SBDIP
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
918
Spec Number 518058
File Number 3042.1




HS-82C37ARH pdf, 반도체, 판매, 대치품
HS-82C37ARH
Pin Descriptions (Continued)
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
A4-A7
37-40
O Address: The four most significant address lines are three-state outputs and provide 4 bits of address.
These lines are enabled only during the Active cycle.
HRQ 10 O Hold Request: The Hold Request (HRQ) output is used to request control of the system bus. When a
DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made, the HS-
82C37ARH issues HRQ. The HLDA signal then informs the controller when access to the system bus-
ses is permitted. For stand-alone operation where the HS-82C37ARH always controls the busses, HRQ
may be tied to HLDA. This will result in one S0 state before the transfer.
DACK0- 14,15, 24,
DACK3
25
O DMA Acknowledge: DMA acknowledge is used to notify the individual peripherals when one has been
granted a DMA cycle. The sense of these lines is programmable. Reset initializes them to active low.
AEN 9 O Address Enable: Address Enable enables the 8-bit latch containing the upper 8 address bits onto the
system address bus. AEN can also be used to disable other system bus drivers during DMA transfers.
AEN is active HIGH.
ADSTB
8
O Address Strobe: This is an active high signal used to control latching of the upper address byte. It will
drive directly the strobe input of external transparent octal latches, such as the 82C82. During block op-
erations, ADSTB will only be issued when the upper address byte must be updated, thus speeding op-
eration through elimination of S1 states. (See Note 2).
MEMR
3
O Memory Read: The Memory Read signal is an active low three-state output used to access data from
the selected memory location during a DMA Read or a Memory-to-Memory transfer.
MEMW
4
O Memory Write: The Memory Write is an active low three-state output used to write data to the selected
memory location during a DMA Write or a Memory-to-Memory transfer.
NC 5
No connect. Pin 5 is open and should not be tested for continuity.
Spec Number 518058
921

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HS-82C37ARH 전자부품, 판매, 대치품
Specifications HS-82C37ARH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
VCC = +5V ±10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range.
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
TEMPERATURE SUBGROUP
LIMITS
MIN MAX
DMA (MASTER) MODE (Continued)
DB Float to Active Delay from
CLK HIGH
TCHDV VDD = 4.5V
HLDA Valid to CLK HIGH Setup TRAVCH VDD = 4.5V
Time
Input Data from MEMR HIGH
Hold Time
TMRHDX VDD = 4.5V
Input Data to MEMR HIGH
Setup Time
TDVMRH VDD = 4.5V
Output Data from MEMW HIGH TMWHDZ VDD = 4.5V
HOLD Time
Output Data Valid to MEMW
HIGH
TDVMWH VDD = 4.5V
DREQ to CLK LOW (SI, S4)
Setup Time
TDQVCL VDD = 4.5V
CLK LOW to READY Hold Time TCLRYX VDD = 4.5V
READY to CLK LOW Setup
Time
ADSTB HIGH from CLK LOW
Delay Time
ADSTB LOW from CLK LOW
Delay Time
READ HIGH Delay from WRITE
HIGH
READ Pulse Width, Normal
Timing
ADSTB Pulse Width
TRYVCL VDD = 4.5V
TCLSH VDD = 4.5V
TCLSL VDD = 4.5V
TWHRH VDD = 4.5V
TRLRH1 VDD = 4.5V
TSHSL VDD = 4.5V
Extended WRITE Pulse Width TWLWH1 VDD = 4.5V
WRITE Pulse Width
TWLWH2 VDD = 4.5V
READ Pulse Width,
Compressed
TRLRH2 VDD = 4.5V
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
9, 10, 11 - 110
9, 10, 11
75
-
9, 10, 11
0
9, 10, 11
155
9, 10, 11
15
9, 10, 11
9, 10, 11
TCLCL-
35
0
-
-
9, 10, 11
20
-
9, 10, 11
60
-
9, 10, 11
-
80
9, 10, 11 - 120
9, 10, 11
0
-
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
2TCLCL
-50
TCLCL -
80
2TCLCL
-100
TCLCL -
100
TCLCL -
50
-
-
-
-
-
PERIPHERAL (SLAVE) MODE
ADR Valid or CS LOW to IOR
LOW
ADR Valid or CS LOW to IOW
LOW Setup Time 0
Data Valid to IOW HIGH Setup
Time
TAVIRL VDD = 4.5V
TAVIWL VDD = 4.5V
TDVIWH VDD = 4.5V
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
9, 10, 11
9, 10, 11
9, 10, 11
10
0
150
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Spec Number 518058
924

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부품번호상세설명 및 기능제조사
HS-82C37ARH

Radiation Hardened CMOS High Performance Programmable DMA Controller

Intersil Corporation
Intersil Corporation

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