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HS-82C54RH 데이터시트 PDF




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부품번호 HS-82C54RH 기능
기능 Radiation Hardened CMOS Programmable Interval Timer
제조업체 Intersil Corporation
로고 Intersil Corporation 로고


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HS-82C54RH 데이터시트, 핀배열, 회로
HS-82C54RH
August 1995
Radiation Hardened CMOS
Programmable Interval Timer
Features
Pinouts
• Radiation Hardened
- Total Dose > 105 RAD (Si)
- Transient Upset > 108 RAD (Si)/sec
- Latch Up Free EPI-CMOS
- Functional After Total Dose 1 x 106 RAD (Si)
• Low Power Consumption
- IDDSB = 20µA
- IDDOP = 12mA
• Pin Compatible with NMOS 8254 and the Intersil 82C54
• High Speed, “No Wait State” Operation with 5MHz
HS-80C86RH
• Three Independent 16-Bit Counters
• Six Programmable Counter Modes
• Binary or BCD Counting
• Status Read Back Command
• Hardened Field, Self-Aligned, Junction Isolated CMOS Process
• Single 5V Supply
• Military Temperature Range -55oC to +125oC
Description
The Intersil HS-82C54RH is a high performance, radiation hardened
CMOS version of the industry standard 8254 and is manufactured
using a hardened field, self-aligned silicon gate CMOS process. It has
three independently programmable and functional 16-bit counters,
each capable of handling clock input frequencies of up to 5MHz. Six
programmable timer modes allow the HS-82C54RH to be used as an
event counter, elapsed time indicator, a programmable one-shot, or
for any other timing application. The high performance, radiation
hardness, and industry standard configuration of the HS-82C54RH
make it compatible with the HS-80C86RH radiation hardened micro-
processor.
Static CMOS circuit design insures low operating power. The Intersil
hardened field CMOS process results in performance equal to or
greater than existing radiation resistant products at a fraction of the
power.
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL
PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
CLK 0 9
OUT 0 10
GATE 0 11
GND 12
24 VDD
23 WR
22 RD
21 CS
20 A1
19 A0
18 CLK 2
17 OUT 2
16 GATE 2
15 CLK 1
14 GATE 1
13 OUT 1
24 LEAD CERAMIC METAL SEAL FLATPACK
PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24
TOP VIEW
D7
D6
D5
D4
D3
D2
D1
D0
CLK 0
OUT 0
GATE 0
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VDD
23 WR
22 RD
21 CS
20 A1
19 A0
18 CLK 2
17 OUT 2
16 GATE 2
15 CLK 1
14 GATE 1
13 OUT1
Ordering Information
PART NUMBER
HS1-82C54RH-Q
HS1-82C54RH-8
HS1-82C54RH-Sample
HS9-82C54RH-Q
HS9-82C54RH-8
HS9-82C54RH/Sample
HS9-82C54RH/Proto
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
-55oC to +125oC
-55oC to +125oC
+25oC
-55oC to +125oC
PACKAGE
24 Lead SBDIP
24 Lead SBDIP
24 Lead SBDIP
24 Lead Ceramic Flatpack
24 Lead Ceramic Flatpack
24 Lead Ceramic Flatpack
24 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
948
Spec Number 518059
File Number 3043.1




HS-82C54RH pdf, 반도체, 판매, 대치품
Specifications HS-82C54RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
AC’s Tested at Worst Case VDD (s), Guaranteed Over Full Operating Range.
PARAMETER
SYMBOL CONDITIONS
Command Recovery Time
TRHRL VDD = 4.5V
WRITE CYCLE
Address Stable Before WR
TAVWL VDD = 4.5V
CS Stable Before WR
TSLWL VDD = 4.5V
Address Hold Time After WR
TWHAX VDD = 4.5V
WR Pulse Width
TWLWH VDD = 4.5V
Data Setup Time Before WR
TDVWH VDD = 4.5V
Data Hold Time After WR
TWHDX VDD = 4.5V
Command Recovery Time
TWHWL VDD = 4.5V
CLOCK AND GATE
Clock Period
TCLCL VDD = 4.5V
High Pulse Width
TCHCL VDD = 4.5V
Low Pulse Width
TCLCH VDD = 4.5V
Gate Width High
TGHGL VDD = 4.5V
Gate Width Low
TGLGH VDD = 4.5V
Gate Setup Time to CLK
TGVCH VDD = 4.5V
Gate Hold Time After CLK
TCHGX VDD = 4.5V
Output Delay from CLK
TCLOV VDD = 4.5V
Output Delay from Gate
TGLOV VDD = 4.5V
Data Delay from Address Read TAVAV VDD = 4.5V
Output Delay from WR High
TWHOV VDD = 4.5V
GROUP A
SUBGROUPS
9, 10, 11
TEMPERATURE
-55oC, +25oC, +125oC
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
LIMITS
MIN MAX UNITS
320 -
ns
0-
0-
0-
240 -
225 -
35 -
320 -
ns
ns
ns
ns
ns
ns
ns
200 -
100 -
100 -
80 -
80 -
80 -
80 -
- 240
- 200
- 275
- 260
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Input Capacitance
Output Capacitance
I/O Capacitance
SYMBOL
CONDITIONS
CIN VDD = Open, f = 1MHz,
All measurements referenced to device ground.
COUT
VDD = Open, f = 1MHz,
All measurements referenced to device ground.
COUT
VDD = Open, f = 1MHz,
All measurements referenced to device ground.
TEMPERATURE
TA = +25oC
TA = +25oC
TA = +25oC
MIN MAX UNITS
- 15 pF
- 15 pF
- 20 pF
TIMING REQUIREMENTS
RD/ to Data Float
TRHDZ VDD = 4.5V and 5.5V
-55oC < TA < +125oC
8
145
ns
TIMING RESPONSES
Clock Rise Time
Clock Fall Time
TCH1CH2 VDD = 4.5V and 5.5V, 1.0V to 3.5V
TCL1CL2 VDD = 4.5V and 5.5V, 3.5V to 1.0V
-55oC < TA < +125oC
-
25
ns
-55oC < TA < +125oC
-
25
ns
NOTE: The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are character-
ized upon initial design release and upon design changes which would affect these characteristics.
Spec Number 518059
951

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HS-82C54RH 전자부품, 판매, 대치품
HS-82C54RH
Intersil Space Level Product Flow -8
GAMMA Radiation Verification (Each Wafer) Method 1019,
2 Samples/Wafer, 0 Rejects
100% Dynamic Burn-In, Condition D, 160 Hours, +125oC or
Equivalent, Method 1015
100% Die Attach
100% Interim Electrical Test
Periodic- Wire Bond Pull Monitor, Method 2011
100% PDA, Method 5004 (Note 1)
Periodic- Die Shear Monitor, Method 2019 or 2027
100% Final Electrical Test
100% Internal Visual Inspection, Method 2010, Condition B 100% Fine/Gross Leak, Method 1014
CSI an/or GSI PreCap (Note 5)
100% External Visual, Method 2009
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% External Visual
100% Initial Electrical Test
Sample - Group A, Method 5005 (Note 2)
Sample - Group B, Method 5005 (Note 3)
Sample - Group C, Method 5005 (Notes 3 and 4)
Sample - Group D, Method 5005 (Notes 3 and 4)
100% Data Package Generation (Note 6)
CSI and/or GSI Final (Note 5)
NOTES:
1. Failures from subgroup 1, 7 are used for calculating PDA. The maximum allowable PDA = 5%.
2. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
3. Group B, C and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include
separate line items for Group B Test, Group C Test, Group C Samples, Group D Test and Group D Samples.
4. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When
required, the P.O. should include a separate line item for Group C Generic Data and/or Group D Generic Data. Generic data is not guar-
anteed to be available and is therefore not available in all cases.
5. CSI and/or GSI inspections are optional and will not be performed unless required by theP.O. When required, the P.O. should include
separate line items for CSI PreCap inspection, CSI final inspection, GSI PreCap inspection, and/or GSI final inspection.
6. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quan-
tity).
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Group B, C and D attributes and/or Generic data is included when required by the P.O.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number 518059
954

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관련 데이터시트

부품번호상세설명 및 기능제조사
HS-82C54RH

Radiation Hardened CMOS Programmable Interval Timer

Intersil Corporation
Intersil Corporation

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