PDF HS-82C85RH Data sheet ( Hoja de datos )

Número de pieza	HS-82C85RH
Descripción	Radiation Hardened CMOS Static Clock Controller/Generator
Fabricantes	Intersil Corporation
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HS-82C85RH August 1995 Radiation Hardened CMOS Static Clock Controller/Generator Features Pinouts • Radiation Hardened - Total Dose > 105 RAD (Si) - Transient Upset > 108 RAD (Si)/s - Latch Up Free EPI-CMOS • Very Low Power Consumption • Pin Compatible with NMOS 8285 and Intersil 82C85 • Generates System Clocks for Microprocessors and Peripherals • Complete Control Over System Clock Operation for Very Low System Power - Stop-Oscillator - Stop-Clock - Low Frequency (Slo) Mode - Full Speed Operation • DC to 15MHz Operation (DC to 5MHz System Clock) • Generates Both 50% and 33% Duty Cycle Clocks (Synchronized) • Uses Either Parallel Mode Crystal Circuit or External Frequency Source • Hardened Field, Self-Aligned, Junction Isolated CMOS Process • Single 5V Supply • Military Temperature Range -55oC to +125oC Description The Intersil HS-82C85RH is a high performance, radiation hardened CMOS Clock Controller/Generator designed to support systems utilizing radiation hardened static CMOS microprocessors such as the HS-80C86RH. The HS-82C85RH contains a crystal controlled oscillator, reset pulse conditioning, halt/restart logic, and divide-by-256 circuitry. These features provide the means to stop the system clock, stop the clock oscillator, or run the system at a low frequency (CLK/256), enhancing control of static system power dissipation and allowing system shut-down during periods of external stress. Static CMOS circuit design insures low operating power and permits operation with an external frequency source from DC to 15MHz. Crystal controlled operation to 15MHz is guaranteed with the use of a parallel, fundamental mode crystal and two small load capacitors. Outputs are guaranteed compatible with both CMOS and TTL speciﬁcations. The Inter- sil hardened ﬁeld CMOS process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW CSYNC 1 PCLK 2 AEN1 3 RDY1 4 READY 5 RDY2 6 AEN2 7 CLK 8 GND 9 CLK50 10 START 11 SLO/FST 12 24 VDD 23 X1 22 X2 21 ASYNC 20 EFI 19 F/C 18 OSC 17 RES 16 RESET 15 S2/STOP 14 S1 13 S0 24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 TOP VIEW CSYNC PCLK AEN1 RDY1 READY RDY2 AEN2 CLK GND CLK50 START SLO/FST 1 2 3 4 5 6 7 8 9 10 11 12 24 VDD 23 X1 22 X2 21 ASYNC 20 EFI 19 F/C 18 OSC 17 RES 16 RESET 15 S2/STOP 14 S1 13 S0 Ordering Information PART NUMBER HS1-82C85RH-Q HS1-82C85RH-8 HS1-82C85RH/Sample HS9-82C85RH/Proto HS9-82C85RH-Q HS9-82C85RH-8 HS9-82C85RH/Sample TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC -55oC to +125oC -55oC to +125oC -55oC to +125oC +25oC PACKAGE 24 Lead SBDIP 24 Lead SBDIP 24 Lead SBDIP 24 Lead Ceramic Flatpack 24 Lead Ceramic Flatpack 24 Lead Ceramic Flatpack 24 Lead Ceramic Flatpack CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 992 Spec Number 518061 File Number 3044.1 1 page Speciﬁcations HS-82C85RH TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS VDD = 4.5V, TA = -55oC to +125oC PARAMETER GROUP A SYMBOL CONDITIONS SUBGROUP TEMPERATURE LIMITS MIN MAX TIMING REQUIREMENTS External Frequency High Time External Frequency Low Time EFI or Crystal Period External Frequency Input Duty Cycle Crystal Frequency RDY1, RDY2 Active Setup to CLK RDY1, RDY2 Active Setup to CLK RDY1, RDY2 Inactive Setup to CLK RDY1, RDY2 Hold to CLK ASYNC Setup to CLK ASYNC Hold to CLK AEN1, AEN2 Setup to RDY1, RDY2 AEN1, AEN2 Hold to CLK CSYNC Setup to EFI CSYNC Hold to EFI CSYNC Pulse Width RES Setup to CLK S0, S1, S2/STOP Setup to CLK S0, S1, S2/STOP Hold to CLK RES, START Setup to CLK RES (Low) or START (High) Pulse Width SLO/FST Setup to PCLK TEHEL TELEH TELEL TEFIDC 90% - 90% VIN 10% - 10% VIN FX TR1VCL TR1VCH ASYNC = High ASYNC = Low TR1VCL TCLR1X TAYVCL TCLAYX TA1VR1V TCLA1X TYHEH TEHYL TYHYL TI1HCL TSVCH Note 3 TCHSX TRSVCH Note 3 TSHSL TSFPC Note 3 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 -55oC, +25oC, +125oC 25 - -55oC, +25oC, +125oC 25 - -55oC, +25oC, +125oC -55oC, +25oC, +125oC 65 45 - 55 -55oC, +25oC, +125oC -55oC, +25oC, +125oC 2.4 55 15 - -55oC, +25oC, +125oC 55 - -55oC, +25oC, +125oC 55 - -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC 0 84 0 25 - - - - -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC 0 17 17 2TELEL 105 55 - - - - - - -55oC, +25oC, +125oC 55 - -55oC, +25oC, +125oC -55oC, +25oC, +125oC 105 2/3 TCLCL - - -55oC, +25oC, +125oC TEHEL+170 - TIMING RESPONSES CLK/CLK50 Cycle Period CLK HIGH Time CLK LOW CLK50 HIGH Time CLK50 LOW Time PCLK HIGH Time TCLCL TCHCL TCLCH T5CHCL T5CLCH TPHPL 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC 200 (1/3 TCLCL) +3 (2/3 TCLCL) -15 (1/2 TCLCL) -7.5 (1/2 TCLCL) -7.5 TCLCL-20 - - - - - - UNITS ns ns ns % MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Spec Number 518061 996 5 Page HS-82C85RH Waveforms (Continued) CLK RDY1, 2 AEN1, 2 ASYNC READY TCLR1X TR1VCL TA1VR1V TCLR1X TR1VCL TAYVCL TCLA1X TCLAYX TRYHCH TRYLCL FIGURE 3. WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES) EFI CLK CLK50 PCLK S0 TCHSX TSVCH S1 S2/STOP RES START TSTOP TSVCH TCHSX TRSVCH FIGURE 4. CLOCK STOP (F/C HIGH OR F/C LOW) 1002 Spec Number 518061 11 Page

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