PDF HS9-82C54RH Data sheet ( Hoja de datos )

Número de pieza	HS9-82C54RH
Descripción	Radiation Hardened CMOS Programmable Interval Timer
Fabricantes	Intersil Corporation
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No Preview Available ! HS-82C54RH August 1995 Radiation Hardened CMOS Programmable Interval Timer Features Pinouts • Radiation Hardened - Total Dose > 105 RAD (Si) - Transient Upset > 108 RAD (Si)/sec - Latch Up Free EPI-CMOS - Functional After Total Dose 1 x 106 RAD (Si) • Low Power Consumption - IDDSB = 20µA - IDDOP = 12mA • Pin Compatible with NMOS 8254 and the Intersil 82C54 • High Speed, “No Wait State” Operation with 5MHz HS-80C86RH • Three Independent 16-Bit Counters • Six Programmable Counter Modes • Binary or BCD Counting • Status Read Back Command • Hardened Field, Self-Aligned, Junction Isolated CMOS Process • Single 5V Supply • Military Temperature Range -55oC to +125oC Description The Intersil HS-82C54RH is a high performance, radiation hardened CMOS version of the industry standard 8254 and is manufactured using a hardened ﬁeld, self-aligned silicon gate CMOS process. It has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies of up to 5MHz. Six programmable timer modes allow the HS-82C54RH to be used as an event counter, elapsed time indicator, a programmable one-shot, or for any other timing application. The high performance, radiation hardness, and industry standard conﬁguration of the HS-82C54RH make it compatible with the HS-80C86RH radiation hardened micro- processor. Static CMOS circuit design insures low operating power. The Intersil hardened ﬁeld CMOS process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 CLK 0 9 OUT 0 10 GATE 0 11 GND 12 24 VDD 23 WR 22 RD 21 CS 20 A1 19 A0 18 CLK 2 17 OUT 2 16 GATE 2 15 CLK 1 14 GATE 1 13 OUT 1 24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 TOP VIEW D7 D6 D5 D4 D3 D2 D1 D0 CLK 0 OUT 0 GATE 0 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VDD 23 WR 22 RD 21 CS 20 A1 19 A0 18 CLK 2 17 OUT 2 16 GATE 2 15 CLK 1 14 GATE 1 13 OUT1 Ordering Information PART NUMBER HS1-82C54RH-Q HS1-82C54RH-8 HS1-82C54RH-Sample HS9-82C54RH-Q HS9-82C54RH-8 HS9-82C54RH/Sample HS9-82C54RH/Proto TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC -55oC to +125oC -55oC to +125oC +25oC -55oC to +125oC PACKAGE 24 Lead SBDIP 24 Lead SBDIP 24 Lead SBDIP 24 Lead Ceramic Flatpack 24 Lead Ceramic Flatpack 24 Lead Ceramic Flatpack 24 Lead Ceramic Flatpack CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 948 Spec Number 518059 File Number 3043.1 1 page Speciﬁcations HS-82C54RH TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: See +25oC limits in Table 1 and Table 2 for Post RAD limits (Sub Groups 1, 7 and 9). TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER Standby Power Supply Current Output Leakage Current Input Leakage Current Output Low Current TTL Output High Current CMOS Output High Current * Which ever is greater. SYMBOL IDDSB IOZL, IOZH IIH, IIL IOL IOH TTL IOH CMOS DELTA LIMITS ±2µA ±2µA ±200nA ±500µA or 10% of BBI Reading* ±500µA or 10% of BBI Reading* ±20µA or 10% of BBI Reading* TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD TESTED FOR -Q RECORDED FOR -Q TESTED FOR -8 Initial Test 100% 5004 1, 7, 9 1 (Note 2) 1, 7, 9 Interim Test 100% 5004 1, 7, 9, ∆ 1, ∆ (Note 2) 1, 7, 9 PDA 100% 5004 1, 7, ∆ - 1, 7 Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 - 2, 3, 8A, 8B, 10, 11 Group A (Note 1) Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆ 1, 2, 3, ∆ (Note 2) N/A Subgroup B6 Sample 5005 1, 7, 9 - N/A Group C Sample 5005 N/A N/A 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group D Sample 5005 1, 7, 9 - 1, 7, 9 Group E, Subgroup 2 Sample 5005 1, 7, 9 - 1, 7, 9 NOTES: 1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised. 2. Table 5 parameters only RECORDED FOR -8 Spec Number 518059 952 5 Page INTERNAL BUS CONTROL WORD REGISTER STATUS LATCH STATUS REGISTER CRM CRL CONTROL LOGIC GATE N CLK N OUT N CE OLM OLL HS-82C54RH Basically, the select inputs A0, A1 connect to the A0, A1 address bus signals of the CPU. The CS can be derived directly from the address bus using a linear select method or it can be connected to the output of a decoder, such as a Intersil HD-6440 for larger systems. A1 A0 ADDRESS BUS (16) CONTROL BUS DATA BUS (8) 8 I/OR I/OW A1 A0 CS COUNTER 0 OUT GATE CLK D0-D7 HS-82C54RH COUNTER 1 OUT GATE CLK RD WR COUNTER 2 OUT GATE CLK FIGURE 7. COUNTER INTERNAL BLOCK DIAGRAM The Status Register, shown in the ﬁgure, when latched, contains the current contents of the Control Word Register and status of the output and null count ﬂag. (See detailed explanation of the Read-Back Command.) The actual counter is labeled CE for “Counting Element”. It is a 16-bit presettable synchronous down counter. OLM and OLL are two 8-bit latches. OL stands for “Output Latch”, subscripts M and L for “Most signiﬁcant byte” and “Least signiﬁcant byte”, respectively. Both are normally referred to as one unit and called just OL. These latches normally “follow” the CE, but if a suitable Counter Latch Command is sent to the HS-82C54RH, the OL latches the present count until read by the CPU and then returns to “following” the CE. One latch at a time is enabled by the counter’s Control Logic to drive the internal bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE itself cannot be read; whenever you read the count, it is the OL that is being read. Similarly, there are two 8-bit registers called CRM and CRL (for “Count Register”). Both are normally referred to as one unit and called just CR. When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transferred to the CE simultaneously. CRM and CRL are cleared when the Counter is programmed for one byte counts (either most signiﬁcant byte only or least signiﬁcant byte only) the other byte will be zero. Note that the CE cannot be written into; whenever a count is written, it is written into the CR. The Control Logic is also shown in the diagram. CLKn, GATEn, and OUTn are all connected to the outside world through the Control Logic. HS-82C54RH System Interface The HS-82C54RH is treated by the system software as an array of peripheral I/O ports; three are Counters and the fourth is a Control Word Register for MODE programming. FIGURE 8. HS-82C54RH SYSTEM INTERFACE Operational Description General After power-up, the state of the HS-82C54RH is undeﬁned. The Mode, count value, and output of all Counters are undeﬁned. How each Counter operates is determined when it is programmed. Each Counter must be programmed before it can be used. Unused Counters need not be programmed. Programming The HS-82C54RH Counters are programmed by writing a Control Word and then an initial count. All Control Words are written into the Control Word Register, which is selected when A1, A0 = 11. The Control Word speciﬁes which Counter is being programmed. By contrast, initial counts are written into the Counters, not the Control Word Register. The A1, A0 inputs are used to select the Counter to be written into. The format of the initial count is determined by the Control Word used. Write Operations The programming procedure for the HS-82C54RH is very ﬂexible. Only two conventions need to be remembered: 1. For each Counter, the Control Word must be written before the initial count is written. 2. The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). Since the Control Word Register and the three Counter shave separate addresses (selected by the A1, A0 inputs), and each Control Word speciﬁes the Counter it applies to (SC0, SC1 bits), no special instruction sequence is required. Any programming sequence that follows the conventions above is acceptable. Spec Number 518059 958 11 Page

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