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HM-6551883 데이터시트 PDF




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부품번호 HM-6551883 기능
기능 256 x 4 CMOS RAM
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HM-6551883 데이터시트, 핀배열, 회로
HM-6551/883
March 1997
256 x 4 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• Internal Latched Chip Select
• High Noise Immunity
• On-Chip Address Register
• Latched Outputs
• Three-State Output
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous cir-
cuit design techniques are employed to achieve high perfor-
mance and low power operation. On chip latches are
provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6551/883 is a fully static RAM and may be main-
tained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
220ns
-55oC to +125oC
HM-6551B/883
300ns
HM1-6551/883
PKG. NO.
F22.4
Pinout
HM-6551/883 (CERDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
GND 8
D0 9
Q0 10
D1 11
22 VCC
21 A4
20 W
19 S1
18 E
17 S2
16 Q3
15 D3
14 Q2
13 D2
12 Q1
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
D Data Input
Q Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-101
File Number 2988.1




HM-6551883 pdf, 반도체, 판매, 대치품
HM-6551/883
TABLE 2. HM-6551/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
Chip Enable
Access Time
(1) TELQV
Address Access
Time
(2) TAVQV
Chip Select 1
Output Enable
Time
(3) TS1LQX
Write Enable
Output Disable
Time
(4) TWLQZ
Chip Select 1
Output Disable
Time
(5) TS1HQZ
Chip Enable Pulse (6) TELEH
Negative Width
Chip Enable Pulse (7) TEHEL
Positive Width
Address Setup
Time
(8) TAVEL
Chip Select 2
Setup Time
(9) TS2LEL
Address Hold Time (10) TELAX
Chip Select 2 Hold (11) TELS2X
Time
Data Setup Time (12) TDVWH
Data Hold Time (13) TWHDX
Chip Select 1 Write (14) TWLS1H
Pulse Setup Time
Chip Enable Write (15) TWLEH
Pulse Setup Time
Chip Select 1 Write (16) TS1LWH
Pulse Hold Time
Chip Enable Write (17) TELWH
Pulse Hold Time
Write Enable Pulse (18) TWLWH
Width
Read or Write
Cycle Time
(19) TELEL
(NOTES 1, 2)
CONDITIONS
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V, Note 3
VCC = 4.5 and
5.5V
GROUP A
SUB-
GROUPS
9, 10, 11
9, 10, 11
9, 10, 11
TEMPERATURE
-55oC TA +125oC
-55oC TA +125oC
-55oC TA +125oC
LIMITS
HM-6551B/883 HM-6551/883
MIN MAX MIN MAX
- 220 - 300
- 220 - 300
5-5-
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC
-
130
-
150
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC
-
130
-
150
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 220 - 300 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 100 - 100 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 0 - 0 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 0 - 0 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 40 - 50 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 40 - 50 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 100 - 150 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 0 - 0 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 120 - 180 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 120 - 180 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 120 - 180 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 120 - 180 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 120 - 180 -
5.5V
VCC = 4.5 and 9, 10, 11 -55oC TA +125oC 320 - 400 -
5.5V
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
IOL = 1.6mA, IOH = -0.4mA, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
6-104

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HM-6551883 전자부품, 판매, 대치품
Timing Waveforms (Continued)
(8) TAVEL
A
TEHEL (7)
E
(9) TS2LEL
S2
HM-6551/883
(10)
TELAX
VALID
TELS2X
(11)
TELEL (19)
TELEH (6)
(8) TAVEL
TEHEL (7)
NEXT
(9) TS2LEL
D
W
S1
TIME
REFERENCE
DATA VALID
TWLEH (15)
TELWH (17)
TDVWH (12)
TWLWH (18)
TS1LWH (16)
TWLS1H (14)
TWHDX (13)
-1 0 1
FIGURE 2. WRITE CYCLE
23
45
TIME
REFERENCE
-1
0
1
2
3
4
5
E
H
L
L
H
TRUTH TABLE
INPUTS
OUTPUTS
S1 S2 W A D
Q
FUNCTION
HXXXX
Z Memory Disabled
XLXVX
Z Cycle Begins, Addresses and S2 are
Latched
LX
XX
Z Write Period Begins
LX
XV
Z Data In is Written
XXHXX
Z Write is Completed
HXXXX
Z Prepare for Next Cycle (Same as -1)
XLXVX
Z Cycle Ends, Next Cycle Begins
(Same as 0)
In the Write Cycle the falling edge of E latches the addresses
and S2 into on-chip registers. S2 must be latched in the low
state to enable the device. The write portion of the cycle is
defined as E, W, S1 being low and S2 being latched simulta-
neously. The W line may go low at any time during the cycle
providing that the write pulse setup times (TWLEH and
TWLS1H) are met. The write portion of the cycle is terminated
on the first rising edge of either E, W, or S1.
If a series of consecutive write cycles are to be executed, the
W line may be held low until all desired locations have been
written. If this method is used, data setup and hold times must
be referenced to the first rising edge of E or S1. By positioning
the write pulse at different times within the E and S1 low time
(TELEH), various types of write cycles may be performed. If
the S1 low time (TS1LS1H) is greater than the W pulse, plus
an output enable time (TS1LQX), a combination read-write
cycle is executed. Data may be modified an indefinite number
of times during any write cycle (TELEH).
The HM-6551/883 may be used on a common I/O bus struc-
ture by tying the input and output pins together. The multiplex-
ing is accomplished internally by the W line. In the write cycle,
when W goes low, the output buffers are forced to a high
impedance state. One output disable time delay (TWLQZ)
must be allowed before applying input data to the bus.
6-107

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관련 데이터시트

부품번호상세설명 및 기능제조사
HM-6551883

256 x 4 CMOS RAM

Intersil Corporation
Intersil Corporation

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