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부품번호 | HM-6642 기능 |
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기능 | 512 x 8 CMOS PROM | ||
제조업체 | Intersil Corporation | ||
로고 | |||
전체 8 페이지수
HM-6642
March 1997
512 x 8 CMOS PROM
Features
Description
• Low Power Standby and Operating Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 120/200ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• Field Programmable
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable
The HM-6642 is a 512 x 8 CMOS NiCr fusible link
Programmable Read Only Memory in the popular 24 pin,
byte wide pinout. Synchronous circuit design techniques
combine with CMOS processing to give this device high
speed performance with very low power dissipation.
On-chip address latches are provided, allowing easy
interfacing with recent generation microprocessors that use
multiplexed address/data bus structures, such as the 8085.
The output enable controls, both active low and active high,
further simplify microprocessor system interfacing by
allowing output data bus control independent of the chip
enable control. The data output latches allow the use of the
HM-6642 in high speed pipelined architecture systems, and
also in synchronous logic replacement functions.
Applications for the HM-6642 CMOS PROM include low
power handheld microprocessor based instrumentation and
communications systems, remote data acquisition and
processing systems, processor control store, and synchro-
nous logic replacement.
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
Ordering Information
PACKAGE
SBDIP
SMD#
SLIM SBDIP
SMD#
CLCC
SMD#
TEMPERATURE RANGE
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
120ns
HM1-6642B-9
5962-8869002JA
HM6-6642B-9
5962-8869002LA
-
5962-88690023A
200ns
HM1-6642-9
5962-8869001JA
HM6-6642-9
5962-8869001LA
HM4-6642-9
5962-88690013A
PKG. NO.
D24.6
D24.6
D24.3
D24.3
J28.A
J28.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 3012.1
HM-6642
Background Information HM-6642 Programming
PROGRAMMING SPECIFICATIONS
SYMBOL
PARAMETER
VCC PROG
Programming VCC
VCCN
Operating VCC
VCC LV
Special Verify VCC
ICC System ICC Capability
ICC Peak
Transient ICC Capability
PROM INPUT PINS
VOL
Output Low Voltage (To PROM)
VOH
Output High Voltage (To PROM)
IOL Output Sink Current (At VOL)
IOH Output Source Current (At VOH)
PROM DATA OUTPUT PINS
VOL
Output Low Voltage (To PROM)
VOH
Output High Voltage (To PROM)
IOL Output Sink Current (At VOL)
IOH Output Source Current (At VOH)
tD Delay Time
tR Rise Time
tF Fall Time
TEHEL
Chip Enable Pulse Width
TAVEL
Address Valid to Chip Enable Low Time
TELQV
Chip Enable Low to Output Valid Time
tpw Programming Pulse Width
tIP Input Leakage at VCC = VCC PROG
TA Ambient Temperature
MIN
12.0
4.5
4.0
500
1.0
-0.3
70% VCC
0.01
0.01
-0.3
70% VCC
3.0
0.5
1.0
1.0
1.0
500
500
-
90
-10
-
LIMITS
TYP
12.0
5.5
-
-
-
GND
VCC
-
-
GND
VCC
-
1.0
1.0
10.0
10.0
-
-
-
100
+1.0
25
MAX
12.5
5.5
6.0
-
-
20% VCC
VCC +0.3
-
-
0.7
VCC +0.3
-
2.0
-
10.0
10.0
-
-
500
110
10
-
UNITS
V
V
V
mA
A
V
V
mA
mA
V
V
mA
mA
µs
µs
µs
ns
ns
ns
µs
µA
oC
6-4
4페이지 HM-6642
Capacitance TA = +25oC
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
CI Input Capacitance (Note 2)
CO Output Capacitance (Note 2)
-
-
10.0 pF f = 1MHz, All Measurements Reference Device
Ground
12.0 pF
NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. Typical derating 5mA/MHz increase in ICCOP.
4. VCC = 4.5V and 5.5V.
Switching Waveform
(9)
TAVEL
(2)
TAVQV
TELAX
(10)
A ADD VALID
TAVEL (9)
NEXT ADD
(8)
TEHEL
E
TELEL (7)
TELEH
(6)
TEHEL (8)
TELQV
(1)
Q
G
(NOTE)
TGXQZ
(5)
TGVQX
(4)
TGVQV
(3)
DATA VALID
TGXQZ (5)
TIME
REFERENCE
-1 0
12
NOTE: G has the same timing as G except signal is inverted.
FIGURE 3. READ CYCLE
3
456
Test Load Circuit
DUT
CL
(NOTE)
NOTE:
TEST HEAD
CAPACITANCE,
INCLUDES STRAY
AND JIG CAPACITANCE
±IOH 1.5V
EQUIVALENT CIRCUIT
IOL
6-7
7페이지 | |||
구 성 | 총 8 페이지수 | ||
다운로드 | [ HM-6642.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
HM-6642 | 512 x 8 CMOS PROM | Intersil Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |