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부품번호 | HM1-6508883 기능 |
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기능 | 1024 x 1 CMOS RAM | ||
제조업체 | Intersil Corporation | ||
로고 | |||
전체 9 페이지수
HM-6508/883
March 1997
1024 x 1 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to
MIL-STD-883 and is Fully Conformant Under the Provi-
sions of Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . .2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 2 TTL Loads
• On-Chip Address Register
The HM-6508/883 is a 1024 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology.
Synchronous circuit design techniques are employed to
achieve high performance and low power operation.
On chip latches are provided for address allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6508/883 is a fully static RAM and may be main-
tained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
PACKAGE TEMP. RANGE 180ns 250ns
CERDIP -55oC to +125oC HM1-
HM1-
6508B/883 6508/883
PKG. NO.
F16.3
Pinout
HM1-6508/883
(CERDIP)
TOP VIEW
E1
A0 2
A1 3
A2 4
A3 5
A4 6
Q7
GND 8
16 VCC
15 D
14 W
13 A9
12 A8
11 A7
10 A6
9 A5
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
D Data Input
Q Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-69
File Number 2985.1
HM-6508/883
TABLE 2. HM-6508/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
Chip Enable
Access Time
(1) TELQV VCC = 4.5 and
5.5V
Address Access
Time
(2) TAVQV VCC = 4.5 and
5.5V, Note 3
Chip Enable
Output Disable
Time
(3) TELQX VCC = 4.5 and
5.5V
Write Enable
Output Disable
Time
(4) TWLQZ VCC = 4.5 and
5.5V
Chip Enable
Output Disable
Time
(5) TEHQZ VCC = 4.5 and
5.5V
Chip Enable
Pulse Negative
Width
(6) TELEH VCC = 4.5 and
5.5V
Chip Enable
Pulse Positive
Width
(7) TEHEL VCC = 4.5 and
5.5V
Address Setup
Time
(8) TAVEL VCC = 4.5 and
5.5V
Address Hold
Time
(9) TELAX VCC = 4.5 and
5.5V
Data Setup Time (10) TDVWH VCC = 4.5 and
5.5V
Data Hold Time
(11) TWHDX VCC = 4.5 and
5.5V
Chip Enable
Write Pulse
Setup Time
(12) TWLEH VCC = 4.5 and
5.5V
Chip Enable
Write Pulse Hold
Time
(13) TELWH VCC = 4.5 and
5.5V
Write Enable
Pulse Width
(14) TWLWH VCC = 4.5 and
5.5V
Read or Write
Cycle Time
(15) TELEL VCC = 4.5 and
5.5V
GROUP A
SUB-
GROUPS
9, 10, 11
TEMPERATURE
-55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
9, 10, 11 -55oC ≤ TA ≤ +125oC
LIMITS
HM-6508B/883 HM-6508/883
MIN MAX MIN MAX UNITS
- 180 - 250 ns
- 180 - 250 ns
5 - 5 - ns
- 120 - 160 ns
- 120 - 160 ns
180 - 250 - ns
100 - 100 - ns
0 - 0 - ns
40 - 50 - ns
80
- 110 -
ns
0 - 0 - ns
100 - 130 - ns
100 - 130 - ns
100 - 130 - ns
280 - 350 - ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); input and output timing reference level: 1.5V; Output load:
1TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
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4페이지 HM-6508/883
TRUTH TABLE
TIME
INPUTS
OUTPUTS
REFERENCE E W A D
Q
FUNCTION
-1
HXXX
Z Memory Disabled
0
XVX
Z Cycle Begins, Addresses are Latched
1L
XX
Z Write Period Begins
2L
XV
Z Data is Written
3
HXX
Z Write Completed
4
HXXX
Z Prepare for Next Cycle (Same as -1)
5
XVX
Z Cycle Ends, Next Cycle Begins (Same as 0)
The write cycle is initiated by the falling edge of E which
latches the address information into the on chip registers.
The write portion of the cycle is defined as both E and W
being low simultaneously. W may go low anytime during the
cycle, provided that the write enable pulse setup time
(TWLEH) is met. The write portion of the cycle is terminated
by the first rising edge of either E or W. Data setup and hold
times must be referenced to the terminating signal.
If a series of consecutive write cycles are to be performed,
the W line may remain low until all desired locations have
been written. When this method is used, data setup and hold
times must be referenced to the rising edge of E. By posi-
tioning the W pulse at different times within the E low time
(TELEH), various types of write cycles may be performed.
If the E low time (TELEH) is greater than the W pulse
(TWLWH), plus an output enable time (TELQX), a combina-
tion read write cycle is executed. Data may be modified an
indefinite number of times during any write cycle (TELEH).
The data input and data output pins may be tied together for
use with a common I/O data bus structure. When using the
RAM in this method, allow a minimum of one output disable
time (TWLQZ) after W goes low before applying input data to
the bus. This will ensure that the output buffers are not active.
Test Load Circuit
DUT
(NOTE 1) CL
IOH
+
-
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE:
1. Test head capacitance includes stray and jig capacitance.
6-75
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부품번호 | 상세설명 및 기능 | 제조사 |
HM1-6508883 | 1024 x 1 CMOS RAM | Intersil Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |