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PDF HMA510GM-75883 Data sheet ( Hoja de datos )
| Número de pieza | HMA510GM-75883 | |
| Descripción | 16 x 16-Bit CMOS Parallel Multiplier Accumulator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HMA510/883
April 1997
16 x 16-Bit CMOS Parallel
Multiplier Accumulator
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 16 x 16-Bit Parallel Multiplication with Accumulation
to a 35-Bit Result
• High-Speed (55ns) Multiply Accumulate Time
• Low Power CMOS Operation
- ICCSB = 500µA Maximum
- ICCOP = 7.0mA Maximum at 1.0MHz
• HMA510/883 is Compatible with the CY7C510 and the
IDT7210
• Supports Two’s Complement or Unsigned Magnitude
Operations
• Three-State Outputs
Ordering Information
PART NUMBER
HMA510GM-55/883
HMA510GM-65/883
HMA510GM-75/883
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 68 Ld CPGA
-55 to 125 68 Ld CPGA
-55 to 125 68 Ld CPGA
PKG.
NO.
G68.B
G68.B
G68.B
Description
The HMA510/883 is a high speed, low power CMOS 16 x
16-bit parallel multiplier accumulator capable of operating at
55ns clocked multiply-accumulate cycles. The 16-bit X and Y
operands may be specified as either two’s complement or
unsigned magnitude format. Additional inputs are provided
for the accumulator functions which include: loading the
accumulator with the current product, adding or subtracting
the accumulator contents and the current product, and pre-
loading the Accumulator Registers from the external inputs.
All inputs and outputs are registered. The registers are all
positive edge triggered, and are latched on the rising edge of
the associated clock signal. The 35-bit Accumulator Output
Register is broken into three parts. The 16-bit least signifi-
cant product (LSP), the 16-bit most significant product
(MSP), and the 3-bit extended product (XTP) Registers. The
XTP and MSP Registers have dedicated output ports, while
the LSP Register shares the Y-inputs in a multiplexed fash-
ion. The entire 35-bit Accumulator Output Register may be
preloaded at any time through the use of the bidirectional
output ports and the preloaded control.
Block Diagram
X0-15
16
RND SUB Y0-15 P0-15
TC ACC
16
PRELOAD
CLKP
REGISTER
REGISTER
REGISTER
CLKY
CLKX
XTP REGISTER
MULTIPLIER ARRAY
35
ACCUMULATOR
MSP REGISTER LSP REGISTER
3 16
35
16
OEX
OEM
OEL
P32-34
P16-31
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-10
File Number 2807.2
1 page  
HMA510/883
TABLE 2. HMA510/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
-55 -65 -75
(NOTE 5)
GROUP A
PARAMETER SYMBOL CONDITIONS SUBGROUPS TEMPERATURE (oC) MIN MAX MIN MAX MIN MAX UNITS
Clock HIGH
Pulse Width
tPWH
9, 10, 11
-55 ≤ TA ≤ 125
20 - 25 - 25 -
ns
Clock LOW
Pulse Width
tPWL
9, 10, 11
-55 ≤ TA ≤ 125
20 - 25 - 25 -
ns
Output Delay
Three-State
Enable Time
tD
tENA
(Note 5)
9, 10, 11
9, 10, 11
-55 ≤ TA ≤ 125
-55 ≤ TA ≤ 125
- 30 - 35 - 35 ns
- 30 - 30 - 35 ns
NOTES:
5. AC Testing as follows: VCC = 4.5V and 5.5V. Input levels 0V and 3.0V (0V and 3.2V tor clock inputs). Timing reference levels = 1.5V,
Output load per test load circuit, with V1 = 2.4V, R1 = 500Ω and CL = 40pF.
6. Transition is measured at 1200mV from steady state voltage, Output loading per test load circuit, with V1 = 1.5V, R1 = 500Ω and CL =
40pF.
TABLE 3. HMA510/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER
TEST
SYMBOL CONDITIONS
NOTE
-55 -65 -75
TEMPERATURE (oC) MIN MAX MIN MAX MIN MAX UNITS
lnput Capacitance
CIN VCC = Open,
f = 1MHz All mea-
surements are ref-
erenced to device
GND
1
TA = 25
- 10 - 10 - 10 pF
Output Capacitance
I/O Capacitance
Input Hold Time
Three-State Disable
Time
COUT
CI/O
tH
tDIS
1
TA = 25
- 10 - 10 - 10 pF
1
TA = 25
- 15 - 15 - 15 pF
1
-55 ≤ TA ≤ 125
3 - 3 - 3 - ns
1
-55 ≤ TA ≤ 125
- 30 - 30 - 30 ns
Output Rise Time
tr From 0.8V to 2.0V 1
-55 ≤ TA ≤ 125
- 10 - 10 - 10 ns
Output Fall Time
tf From 2.0V to 0.8V 1
-55 ≤ TA ≤ 125
- 10 - 10 - 10 ns
NOTE:
7. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
-
PDA
100%
1
Final Test
100%
2, 3, 8A, 8B, 10,11
Group A
- 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C and D
Samples/5005
1, 7, 9
3-14
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