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PDF CY28346 Data sheet ( Hoja de datos )
| Número de pieza | CY28346 | |
| Descripción | Clock Synthesizer with Differential CPU Outputs | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY28346
Clock Synthesizer with Differential CPU Outputs
Features
• Compliant with Intel® CK 408 Mobile Clock Synthesizer
specifications
• 3.3V power supply
• Three differential CPU clocks
• Ten copies of PCI clocks
Table 1. Frequency Table[1]
S2 S1 S0 CPU (0:2) 3V66
100
66M
66M
1 0 1 100M
66M
1 1 0 200M
66M
1 1 1 133M
66M
000
66M
66M
0 0 1 100M
66M
0 1 0 200M
66M
0 1 1 133M
66M
M0 0
Hi-Z
Hi-Z
M 0 1 TCLK/2 TCLK/4
66BUFF(0:2)/
3V66(0:4)
66IN
66IN
66IN
66IN
66M
66M
66M
66M
Hi-Z
TCLK/4
• 5/6 copies of 3V66 clocks
• SMBus support with read-back capabilities
• Spread Spectrum electromagnetic interference (EMI)
reduction
• Dial-a-Frequency™ features
• Dial-a-dB™ features
• 56-pin TSSOP and SSOP packages
66IN/3V66–5
66-MHz clock input
66-MHz clock input
66-MHz clock input
66-MHZ clock input
66M
66M
66M
66M
Hi-Z
TCLK/4
PCI_FPCI
66IN/2
66IN/2
66IN/2
66IN/2
33 M
33 M
33 M
33 M
Hi-Z
TCLK/8
REF
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
Hi-Z
TCLK
USB/ DOT
48M
48M
48M
48M
48M
48M
48M
48M
Hi-Z
TCLK/2
Block Diagram
XIN
XOUT
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PG#
PCI_STP#
PLL1
PLL2
PD#
SDATA
SCLK
VDDA
WD
Logic
I2C
Logic
Power
Up Logic
Pin Configuration
REF
CPUT(0:2)
CPUC(0:2)
3V66_0
3V66_1/VCH
/2 PCI(0:6)
PCI_F(0:2)
48M USB
48M DOT
66B[0:2]/3V66[2:4]
66IN/3V66-5
VDD
XIN
XOUT
VSS
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCI3
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
VDDA
VSSA
VTT_PG#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 REF
55 S1
54 S0
53 CPU_STP#
52 CPUT0
51 CPUC0
50 VDD
49 CPUT1
48 CPUC1
47 VSS
46 VDD
45 CPUT2
44 CPUC2
43 MULT0
42 IREF
41 VSSIREF
40 S2
39 48MUSB
38 48MDOT
37 VDD
36 VSS
35 3V66_1/VCH
34 PCI_STP#
33 3V66_0
32 VDD
31 VSS
30 SCLK
29 SDATA
Note:
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M= driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a
0 state will be latched into the device’s internal state register.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07331 Rev. *B
Revised December 26, 2002
1 page  
CY28346
Byte 6: Silicon Signature Register[4] (all bits are Read-only)
Bit @Pup Pin#
70
Revision = 0001
60
50
41
30
Vendor Code = 0011
20
11
01
Description
Byte 7: Reserved Register
Bit @Pup
70
60
50
40
30
20
10
00
Pin#
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Description
Byte 8: Dial-a-Frequency Control Register N
Bit @Pup Name
Description
70
Reserved. Set = 0.
6 0 N6, MSB These bits are for programming the PLL’s internal N register. This access allows the user to
5
0 N5
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
4
0 N4
relative to the CPU clock.
3 0 N3
2 0 N2
1 0 N3
0 0 N0, LSB
Byte 9: Dial-a-Frequency Control Register R
Bit @Pup
Name
Description
70
Reserved. Set = 0.
6 0 R5, MSB These bits are for programming the PLL’s internal R register. This access allows the user to
5 0 R4
4 0 R3
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
3 0 R2
2 0 R1
1 0 R0
0
0
DAF_ENB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded
from DAF (SMBus) registers.
Note:
4. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
Document #: 38-07331 Rev. *B
Page 5 of 20
5 Page 
CY28346
PCI_STP# – Deassertion (transition from logic “0”
to logic “1”)
The deassertion of the PCI_STP# signal will cause all PCI(0:6)
and stoppable PCI_F(0:2) clocks to resume running in a
synchronous manner within two PCI clock periods after
PCI_STP# transitions to a HIGH level.
Note. The PCI STOP function is controlled by two inputs. One
is the device PCI_STP# pin number 34 and the other is SMBus
Byte 0,Bit 3. These two inputs to the function are logically
AND’ed. If either the external pin or the internal SMBus
register bit is set LOW, the stoppable PCI clocks will be
stopped in a logic LOW state. Reading SMBus Byte 0,Bit 3 will
return a 0 value if either of these control bits are set LOW
(which indicates that the devices stoppable PCI clocks are not
running).
PD# (Power-down) Clarification
The PD# (power-down) pin is used to shut off all clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO and PLLs are also powered down. All clocks are
shut down in a synchronous manner so has not to cause
glitches while transitioning to the LOW “stopped” state.
PD# – Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock, then on the next HIGH-to-LOW transition
of PCIF, the PCIF clock is stopped LOW. On the next
HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped
LOW. From this time, each clock will stop LOW on its next
HIGH-to-LOW transition, except the CPUT clock. The CPU
clocks are held with the CPUT clock pin driven HIGH with a
value of 2 × Iref, and CPUC undriven. After the last clock has
stopped, the rest of the generator will be shut down.
PD# – Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 3.0 ms.
PCI_STP#
PCI_F(0:2) 33M
PCI(0:6) 33M
t setup
Figure 11. PCI_STP# Assertion Waveform
t setup
PCI_STP#
PCI_F(0:2)
PCI(0:6)
Figure 12. PCI_STP# Deassertion Waveform
Document #: 38-07331 Rev. *B
Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CY28346.PDF ] | |
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