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PDF CY62148 Data sheet ( Hoja de datos )
| Número de pieza | CY62148 | |
| Descripción | 512K x 8 MoBL Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY62148 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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1CY 621 48
www.DataSheet4U.com
fax id: 1079
PRELIMINARY
CY62148
Features
• 4.5V−5.5V operation
• CMOS for optimum speed/power
• Low active power
— 660 mW (max.)
• Low standby power (L version)
— 2.75 mW (max.)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE options
Functional Description
The CY62148 is a high-performance CMOS static RAM orga-
nized as 524,288 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. This device has
Logic Block Diagram
512K x 8 Static RAM
an automatic power-down feature that reduces power con-
sumption by more than 99% when deselected.
Writing to the device is accomplished by taking chip enable
one (CE) and write enable (WE) inputs LOW. Data on the eight
I/O pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking chip en-
able one (CE) and output enable (OE) LOW while forcing write
enable (WE). Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148 is available in a standard 450-mil-wide body
width SOIC package.
Pin Configuration
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6 512K x 8
A7 ARRAY
A8
A9
A10
CE
COLUMN
DECODER
POWER
DOWN
WE
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
62148-1
I/O7
Top View
SOIC
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 A18
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Commercial
Commercial
CY62148–55 CY62148–70
55 70
120 mA
120 mA
2 mA
2 mA
L 0.5 mA
0.5 mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1996 - Revised July 31, 1997
1 page  
www.DataSheet4U.com
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13,14]
ADDRESS
CE
tWC
tSCE
CY62148
tAW
tSA tPWE
WE
OE
DATA I/O
NOTE 15
tHZOE
Write Cycle No.3 (WE Controlled, OE LOW)[13,14]
ADDRESS
CE
tSD
DATAIN VALID
tWC
tSCE
tHA
tHD
tSA
WE
tAW
tPWE
DATAI/O NOTE 15
tHZWE
tSD
DATA VALID
Note:
15. During this period the I/Os are in the output state and input signals should not be applied
tHA
tHD
tLZWE
62148-8
62148-9
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CY62148.PDF ] | |
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