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AT27LV520 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AT27LV520
기능 512K 64K x 8 Multiplexed Addresses/ Outputs Low Voltage OTP EPROM
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AT27LV520 데이터시트, 핀배열, 회로
Features
8-Bit Multiplexed Addresses/Outputs
Fast Read Access Time - 90 ns
Dual Voltage Range Operation
– Low-Voltage Power Supply Range, 3.0V to 3.6V, or
– Standard 5V ± 10% Supply Range
Low Power CMOS Operation
– 20 µA max. Standby for ALE = VIH and VCC = 3.6V
– 29 mW max. Active at 5 MHz for VCC = 3.6V
20-Lead TSSOP Package
High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
RapidProgramming Algorithm - 50 µs/byte (typical)
CMOS and TTL Compatible Inputs and Outputs
– JEDEC Standard for LVTTL
Integrated Product Identification Code
Commercial and Industrial Temperature Range
Description
The AT27LV520 is a low-power, high-performance 524,288-bit one-time programma-
ble read only memory (OTP EPROM) organized 64K by 8 bits. It incorporates latches
for the 8 lower order address bits to multiplex with the 8 data bits. This minimizes sys-
tem chip count, reduces cost, and simplifies the design of multiplexed bus systems. It
requires only one power supply in the range of 3.0V to 3.6V for normal read mode
operation, making it ideal for fast, portable systems using battery power. Any byte can
be accessed in less than 90 ns.
The AT27LV520 is available in 173 mil, 20-pin TSSOP, 300 mil, 20-pin SOIC and 28-
pin TSOP, one-time programmable (OTP) plastic packages.
(continued)
Pin Configurations
TSSOP Top View
Pin Name Function
A8 - A15
AD0 - AD7
OE /VPP
ALE
Addresses
Addresses/Outputs
Output Enable/VPP
Address Latch Enable
A10
A12
A14
ALE
VCC
OE/VPP
A15
A13
A11
A9
1
2
3
4
5
6
7
8
9
10
20 A8
19 AD1
18 AD3
17 AD5
16 AD7
15 GND
14 AD6
13 AD4
12 AD2
11 AD0
TSOP Top View
A10
NC
NC
A12
A14
ALE
VCC
OE/VPP
A15
A13
A11
NC
NC
A9
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21 A8
20 NC
19 NC
18 AD1
17 AD3
16 AD5
15 AD7
14 GND
13 AD6
12 AD4
11 AD2
10 NC
9 NC
8 AD0
SOIC Top View
OE/VPP
A15
A13
A11
A9
AD0
AD2
AD4
AD6
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 ALE
18 A14
17 A12
16 A10
15 A8
14 AD1
13 AD3
12 AD5
11 AD7
512K (64K x 8)
Multiplexed
Addresses/
Outputs
Low Voltage
OTP EPROM
AT27LV520
Rev. 0911B-B–01/98
1




AT27LV520 pdf, 반도체, 판매, 대치품
DC and AC Operating Conditions for Read Operation
AT27LV520-90
Operating Temp. (Case)
Com.
Ind.
0°C - 70°C
-40°C - +85°C
VCC Supply
3.0V to 3.6V
5V ± 10%
DC and Operating Characteristics for Read Operation
Symbol Parameter
Condition
VCC = 3.0V to 3.6V
ILI Input Load Current
VIN = 0V to VCC
ILO
ISB (1)
Output Leakage Current
VCC Standby Current
VOUT = 0V to VCC
ALE = VCC ± 0.3V; Ai, ADi = GND/VCC ± 0.3V
ICC VCC Active Current
f = 5 MHz, IOUT = 0 mA, ALE = VIL
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
IOL = 2.0 mA
VOH Output High Voltage
IOH = -2.0 mA
VCC = 4.5V to 5.5V
ILI Input Load Current
VIN = 0V to VCC
ILO
ISB (1)
Output Leakage Current
VCC Standby Current
VOUT = 0V to VCC
ALE = VCC ± 0.3V; Ai, ADi = GND/VCC ± 0.3V
ICC VCC Active Current
f = 5 MHz, IOUT = 0 mA, ALE = VIL
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
IOL = 2.1 mA
VOH
Note:
Output High Voltage
IOH = -400 µA
VCC standby current will be slightly higher with ALE, Ai, and ADi at TTL levels.
AC Characteristics for Read Operation
VCC = 3.0V to 3.6V and 4.5V to 5.5V
Symbol Parameter
tACC(3)
Address to Output Delay
tCE Address Latch Enable Low to Output Delay
tAS Address Setup Time
tAH
tALE
tOE(3)
tDF(4)(5)
Address Hold Time
Address Latch Enable Width
OE/VPP to Output Delay
OE/VPP High to Output Float
tOH Output Hold from Address or OE/VPP, whichever occurred first
Notes: 2, 3, 4 — see AC Waveforms for Read Operation
4 AT27LV520
Condition
ALE = OE/VPP = VIL
Address Valid
OE/VPP = VIH
OE/VPP = VIH
OE/VPP = VIH
ALE = VIL
ALE = VIL
ALE = VIL
Min Max Units
±1 µA
±5 µA
20 µA
8 mA
-0.6 0.8 V
2.0
VCC + 0.5
V
0.4 V
2.4 V
±1 µA
±5 µA
100 µA
20 mA
-0.6 0.8 V
2.0
VCC + 0.5
V
0.4 V
2.4
AT27LV520-90
Min Max
90
70
15
15
45
35
25
0
Units
ns
ns
ns
ns
ns
ns
ns
ns

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AT27LV520 전자부품, 판매, 대치품
AT27LV520
AC Programming Characteristics*
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, OE/VPP = 13.0 ± 0.25V
Symbol Parameter(1)
Test Conditions
Limits
Min Max
Units
tALE
tLAS
tLAH
tLP
tOES
tOEH
tDS
tDH
tPW
tVR
tVCS
tOE
tDFP
tAS
tAH
tPRT
Address Latch Enable Width
Latched Address Setup Time
Latched Address Hold Time
ALE Low to OE/VPP High Voltage Delay
OE/VPP Setup Time
OE/VPP Hold Time
Data Setup Time
Data Hold Time
ALE Program Pulse Width(2)
OE/VPP Recovery Time
VCC Setup Time
Data Valid from OE/VPP
OE/VPP High to Output Float Delay(4)
Address Setup Time
Input Rise and Fall Times
(10% to 90%) 20 ns
Input Pulse Levels
0.45V to 2.4V
Input Timing Reference Level
0.8V to 2.0V
Output Timing Reference Level
0.8V to 2.0V
Address Hold Time
OE/VPP Pulse Rise Time During
Programming
500
100
100
2
2
2
2
2
47.5
2
2
0
2
0
50
52.5
150
130
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
ns
Notes:
1. VCC must be applied simultaneously or before OE/VPP and removed simultaneously or after OE/VPP.
2. Program Pulse width tolerance is 50 µsec ± 5%.
3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven
— see timing diagram.
Atmel’s 27LV520 Integrated Product Identification Code
Codes
Manufacturer
Device Type
Pins
Hex
A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Data
0 0 0 0 1 1 1 1 0 1E
1 1 0 0 1 1 1 0 1 9D
7

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부품번호상세설명 및 기능제조사
AT27LV520

512K 64K x 8 Multiplexed Addresses/ Outputs Low Voltage OTP EPROM

ATMEL Corporation
ATMEL Corporation
AT27LV520-90

512K 64K x 8 Multiplexed Addresses/ Outputs Low Voltage OTP EPROM

ATMEL Corporation
ATMEL Corporation

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