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AT28BV256 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AT28BV256
기능 256K (32K x 8) Battery-Voltage Parallel EEPROMs
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AT28BV256 데이터시트, 핀배열, 회로
Features
Single 2.7V - 3.6V Supply
Fast Read Access Time – 200 ns
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum
– 1- to 64-byte Page Write Operation
Low Power Dissipation
– 15 mA Active Current
– 20 µA CMOS Standby Current
Hardware and Software Data Protection
Data Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 10,000 Cycles
– Data Retention: 10 Years
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Option Only
256K (32K x 8)
Battery-Voltage
Parallel
EEPROMs
AT28BV256
1. Description
The AT28BV256 is a high-performance electrically erasable and programmable read-
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access
times to 200 ns with power dissipation of just 54 mW. When the device is deselected,
the CMOS standby current is less than 200 µA.
The AT28BV256 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by Data polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28BV256 has additional features to ensure high quality and manufactura-
bility. The device utilizes internal error correction for extended endurance and
improved data retention characteristics. An optional software data protection mecha-
nism is available to guard against inadvertent writes. The device also includes an
extra 64 bytes of EEPROM for device identification or tracking.
0273K–PEEPR–2/09




AT28BV256 pdf, 반도체, 판매, 대치품
5. Device Operation
5.1 Read
The AT28BV256 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their system.
5.2 Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of tWC, a read operation will effectively be a polling operation.
5.3 Page Write
The page write operation of the AT28BV256 allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC
limit is exceeded the AT28BV256 will cease accepting data and commence the internal pro-
gramming operation. All bytes during a page write operation must reside on the same page as
defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page
write operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes
may be loaded in any order and may be altered within the same load period. Only bytes which
are specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.
5.4 Data Polling
The AT28BV256 features Data Polling to indicate the end of a write cycle. During a byte or page
write cycle, an attempted read of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all
outputs, and the next write cycle may begin. Data Polling may begin at anytime during the write
cycle.
5.5 Toggle Bit
In addition to Data Polling, the AT28BV256 provides another method for determining the end of
a write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
5.6 Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel® has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
4 AT28BV256
0273K–PEEPR–2/09

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AT28BV256 전자부품, 판매, 대치품
9. AC Read Characteristics
Symbol
tACC
tCE(1)
tOE(2)
tDF(3)(4)
tOH
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CE or Address, whichever occurred first
10. AC Read Waveforms(1)(2)(3)(4)
AT28BV256
AT28BV256-20
Min Max
200
200
0 80
0 55
0
Units
ns
ns
ns
ns
ns
tCE
tOE
tACC
tDF
tOH
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
0273K–PEEPR–2/09
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AT28BV256

256K (32K x 8) Battery-Voltage Parallel EEPROMs

ATMEL Corporation
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