AT28BV64 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AT28BV64
기능 64K (8K x 8) Battery-Voltage Parallel EEPROMs
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AT28BV64 데이터시트, 핀배열, 회로
2.7V to 3.6V Supply
– Full Read and Write Operation
Low Power Dissipation
– 8 mA Active Current
– 50 µA CMOS Standby Current
Read Access Time – 300 ns
Byte Write – 3 ms
Direct Microprocessor Control
– DATA Polling
– READY/BUSY Open Drain Output
High Reliability CMOS Technology
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
JEDEC Approved Byte-Wide Pinout
Industrial Temperature Ranges
64K (8K x 8)
1. Description
The AT28BV64 is a low-voltage, low-power Electrically Erasable and Programmable
Read-only Memory specifically designed for battery powered applications. Its 64K of
memory is organized 8,192 words by 8 bits. Manufactured with Atmel’s advanced
nonvolatile CMOS technology, the device offers access times to 200 ns with power
dissipation less than 30 mW. When the device is deselected the standby current is
less than 50 µA.
The AT28BV64 is accessed like a Static RAM for the read or write cycles without the
need for external components. During a byte write, the address and data are latched
internally, freeing the microprocessor address and data bus for other operations. Fol-
lowing the initiation of a write cycle, the device will go to a busy state and
automatically clear and write the latched data using an internal control timer. The
device includes two methods for detecting the end of a write cycle, level detection of
RDY/BUSY and DATA polling of I/O7. Once the end of a write cycle has been
detected, a new access for a read or write can begin.
Atmel’s AT28BV64 has additional features to ensure high quality and manufacturabil-
ity. The device utilizes error correction internally for extended endurance and for
improved data retention characteristics. An extra 32-bytes of EEPROM are available
for device identification or tracking.
Not Recommended
for New Designs.

AT28BV64 pdf, 반도체, 판매, 대치품
5. Device Operation
5.1 Read
The AT28BV64 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in a high impedance state whenever CE or OE is high. This dual line control
gives designers increased flexibility in preventing bus contention.
5.2 Byte Write
Writing data into the AT28BV64 is similar to writing into a Static RAM. A low pulse on the WE or
CE input with OE high and CE or WE low (respectively) initiates a byte write. The address loca-
tion is latched on the falling edge of WE (or CE); the new data is latched on the rising edge.
Internally, the device performs a self-clear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated and
for the duration of tWC, a read operation will effectively be a polling operation.
Pin 1 is an open drain READY/BUSY output that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle and is released at the completion of
the write. The open drain connection allows for OR-tying of several devices to the same
RDY/BUSY line.
5.4 DATA Polling
The AT28BV64 provides DATA Polling to signal the completion of a write cycle. During a write
cycle, an attempted read of the data being written results in the complement of that data for I/O7
(the other outputs are indeterminate). When the write cycle is finished, true data appears on all
5.5 Write Protection
Inadvertent writes to the device are protected against in the following ways: (a) VCC sense – if
VCC is below 1.8V (typical) the write function is inhibited; (b) VCC power on delay – once VCC has
reached 2.0V the device will automatically time out 10 ms (typical) before allowing a byte write;
and (c) Write Inhibit – holding any one of OE low, CE high or WE high inhibits byte write cycles.
4 AT28BV64


AT28BV64 전자부품, 판매, 대치품
11. Input Test Waveforms and Measurement Level
tR, tF < 20 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
8 12
1. This parameter is characterized and is not 100% tested.
VIN = 0V


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64K (8K x 8) Battery-Voltage Parallel EEPROMs

ATMEL Corporation
ATMEL Corporation

64K (8K x 8) Battery-Voltage Parallel EEPROM

ATMEL Corporation
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