AT28BV64B PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AT28BV64B
기능 64K (8K x 8) Battery-Voltage Parallel EEPROM
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AT28BV64B 데이터시트, 핀배열, 회로
Single 2.7V to 3.6V Supply
Hardware and Software Data Protection
Low Power Dissipation
– 15mA Active Current
– 20µA CMOS Standby Current
Fast Read Access Time – 200ns
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum
– 1 to 64 Byte Page Write Operation
DATA Polling for End of Write Detection
High-reliability CMOS Technology
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Only
1. Description
The Atmel® AT28BV64B is a high-performance electrically erasable programmable
read only-memory (EEPROM). Its 64K of memory is organized as 8,192 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 200ns with power dissipation of just 54 mW. When the device is
deselected, the CMOS standby current is less than 20µA.
The AT28BV64B is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 64 byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28BV64B has additional features to ensure high quality and manufactur-
ability. A software data protection mechanism guards against inadvertent writes. The
device also includes an extra 64 bytes of EEPROM for device identification or
64K (8K x 8)
with Page Write
and Software
Data Protection

AT28BV64B pdf, 반도체, 판매, 대치품
4.4 DATA Polling
The AT28BV64B features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is valid
on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the
write cycle.
4.5 Toggle Bit
In addition to DATA Polling, the AT28BV64B provides another method for determining the end of
a write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop
toggling and valid data will be read. Reading the toggle bit may begin at any time during the write
4.6 Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
Hardware Protection
Hardware features protect against inadvertent writes to the AT28BV64B in the following ways:
(a) VCC power-on delay – once VCC has reached 1.8V (typical) the device will automatically time
out 10 ms (typical) before allowing a write; (b) write inhibitholding any one of OE low, CE high
or WE high inhibits write cycles; and (c) noise filterpulses of less than 15ns (typical) on the WE
or CE inputs will not initiate a write cycle.
Software Data Protection
A software-controlled data protection feature has been implemented on the AT28BV64B.
Software data protection (SDP) helps prevent inadvertent writes from corrupting the data in the
device. SDP can prevent inadvertent writes during power-up and power-down as well as any
other potential periods of system instability.
The AT28BV64B can only be written using the software data protection feature. A series of three
write commands to specific addresses with specific data must be presented to the device before
writing in the byte or page mode. The same three write commands must begin each write
operation. All software write commands must obey the page mode write timing specifications.
The data in the 3-byte command sequence is not written to the device; the addresses in the
command sequence can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte sequence will start the internal write timers.
No data will be written to the device; however, for the duration of tWC, read operations will effec-
tively be polling operations.
4.7 Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ± 0.5V and using address locations 0000H to 003FH, the additional bytes may
be written to or read from in the same manner as the regular memory array.
4 AT28BV64B


AT28BV64B 전자부품, 판매, 대치품
11. Input Test Waveforms and Measurement Level
tR, tF < 20 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
8 12
1. This parameter is characterized and is not 100% tested.
VIN = 0V


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64K (8K x 8) Battery-Voltage Parallel EEPROMs

ATMEL Corporation
ATMEL Corporation

64K (8K x 8) Battery-Voltage Parallel EEPROM

ATMEL Corporation
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