AT28C64B PDF 데이터시트 ( Data , Function )

부품번호 AT28C64B 기능
기능 64K (8K x 8) Parallel EEPROM
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AT28C64B 데이터시트, 핀배열, 회로
Fast Read Access Time – 150 ns
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum (Standard)
2 ms Maximum (Option – Ref. AT28HC64BF Datasheet)
– 1 to 64-byte Page Write Operation
Low Power Dissipation
– 40 mA Active Current
– 100 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling and Toggle Bit for End of Write Detection
High Reliability CMOS Technology
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
Single 5V ±10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Option Only
1. Description
The AT28C64B is a high-performance electrically-erasable and programmable read-
only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 150 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 100 µA.
The AT28C64B is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA POLLING of I/O7. Once the end of a write cycle has been
detected, a new access for a read or write can begin.
Atmel’s AT28C64B has additional features to ensure high quality and manufacturabil-
ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.
64K (8K x 8)
Page Write and
Software Data

AT28C64B pdf, 반도체, 판매, 대치품
4.4 DATA Polling
The AT28C64B features DATA Polling to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all
outputs, and the next write cycle may begin. DATA Polling may begin at any time during the write
4.5 Toggle Bit
In addition to DATA Polling, the AT28C64B provides another method for determining the end of a
write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle.
4.6 Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel® has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
Hardware Data Protection
Hardware features protect against inadvertent writes to the AT28C64B in the following ways: (a)
VCC sense – if VCC is below 3.8 V (typical), the write function is inhibited; (b) VCC power-on delay
– once VCC has reached 3.8 V, the device will automatically time out 5 ms (typical) before allow-
ing a write; (c) write inhibit – holding any one of OE low, CE high, or WE high inhibits write
cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not ini-
tiate a write cycle.
Software Data Protection
A software controlled data protection feature has been implemented on the AT28C64B. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C64B is shipped from Atmel with SDP dis-
SDP is enabled by the user issuing a series of three write commands in which three specific
bytes of data are written to three specific addresses (see “Software Data Protection Algorithms”
on page 10). After writing the 3-byte command sequence and waiting tWC, the entire AT28C64B
will be protected against inadvertent writes. It should be noted that even after SDP is enabled,
the user may still perform a byte or page write to the AT28C64B by preceding the data to be writ-
ten by the same 3-byte command sequence used to enable SDP.
Once set, SDP remains active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP protects the AT28C64B during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not actually written into the device; their
addresses may still be written with user data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device. However, for the duration of
tWC, read operations will effectively be polling operations.
4.7 Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12V ±0.5V and using address locations 1FC0H to 1FFFH, the additional bytes may be
written to or read from in the same manner as the regular memory array.
4 AT28C64B


AT28C64B 전자부품, 판매, 대치품
11. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
8 12
1. This parameter is characterized and is not 100% tested.
VIN = 0V


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64K (8K x 8) Parallel EEPROMs

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64K (8K x 8) Parallel EEPROM

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