AT28C64E PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AT28C64E
기능 64K (8K x 8) Parallel EEPROMs
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AT28C64E 데이터시트, 핀배열, 회로
Fast Read Access Time – 120 ns
Fast Byte Write – 200 µs
Self-timed Byte Write Cycle
– Internal Address and Data Latches
– Internal Control Timer
– Automatic Clear Before Write
Direct Microprocessor Control
– READY/BUSY Open Drain Output
– DATA Polling
Low Power
– 30 mA Active Current
– 100 µA CMOS Standby Current
High Reliability
– Endurance: 105 Cycles
– Data Retention: 10 Years
5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-Free) Packaging Option
64K (8K x 8)
1. Description
The AT28C64E is a low-power, high-performance 8,192 words by 8-bit nonvolatile
electrically erasable and programmable read-only memory with popular, easy-to-use
features. The device is manufactured with Atmel’s reliable nonvolatile technology.
The AT28C64E is accessed like a Static RAM for the read or write cycles without the
need for external components. During a byte write, the address and data are latched
internally, freeing the microprocessor address and data bus for other operations. Fol-
lowing the initiation of a write cycle, the device will go to a busy state and
automatically clear and write the latched data using an internal control timer. The
device includes two methods for detecting the end of a write cycle, level detection of
RDY/BUSY (unless pin 1 is N.C.) and DATA Polling of I/O7. Once the end of a write
cycle has been detected, a new access for a read or write can begin.
The CMOS technology offers fast access times of 120 ns at low power dissipation.
When the chip is deselected, the standby current is less than 100 µA.
Atmel’s AT28C64E has additional features to ensure high quality and manufacturabil-
ity. The device utilizes error correction internally for extended endurance and for
improved data retention characteristics. An extra 32 bytes of EEPROM are available
for device identification or tracking.

AT28C64E pdf, 반도체, 판매, 대치품
5. Device Operation
5.1 Read
The AT28C64E is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in a high impedance state whenever CE or OE is high. This dual line control
gives designers increased flexibility in preventing bus contention.
5.2 Byte Write
Writing data into the AT28C64E is similar to writing into a Static RAM. A low pulse on the WE or
CE input with OE high and CE or WE low (respectively) initiates a byte write. The address loca-
tion is latched on the falling edge of WE (or CE); the new data is latched on the rising edge.
Internally, the device performs a self-clear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated and
for the duration of tWC, a read operation will effectively be a polling operation.
5.3 Fast Byte Write
The AT28C64E offers a byte write time of 200 µs maximum. This feature allows the entire
device to be rewritten in 1.6 seconds.
Pin 1 is an open drain RDY/BUSY output that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle and is released at the completion of
the write. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY line.
5.5 Data Polling
The AT28C64E provides DATA Polling to signal the completion of a write cycle. During a
write cycle, an attempted read of the data being written results in the complement of that data for
I/O7 (the other outputs are indeterminate). When the write cycle is finished, true data appears on
all outputs.
5.6 Write Protection
Inadvertent writes to the device are protected against in the following ways: (a) VCC sense – if
VCC is below 3.8V (typical), the write function is inhibited; (b) VCC power on delay – once VCC has
reached 3.8V, the device will automatically time out 5 ms (typical) before allowing a byte write;
and (c) write inhibit – holding any one of OE low, CE high or WE high inhibits byte write cycles.
5.7 Chip Clear
The contents of the entire memory of the AT28C64E may be set to the high state by the CHIP
CLEAR operation. By setting CE low and OE to 12 volts, the chip is cleared when a 10 msec low
pulse is applied to WE.
5.8 Device Identification
An extra 32 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12 ± 0.5V and using address locations 1FE0H to 1FFFH the additional bytes may be
written to or read from in the same manner as the regular memory array.
4 AT28C64E


AT28C64E 전자부품, 판매, 대치품
11. Input Test Waveforms and Measurement Level
tR, tF < 20 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
8 12
1. This parameter is characterized and is not 100% tested.
VIN = 0V


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64K (8K x 8) Parallel EEPROMs

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64K (8K x 8) Parallel EEPROM

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