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AT28HC256 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AT28HC256
기능 256K (32K x 8) High-speed Parallel EEPROM
제조업체 ATMEL Corporation
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AT28HC256 데이터시트, 핀배열, 회로
Features
Fast Read Access Time – 70 ns
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
Fast Write Cycle Times
– Page Write Cycle Time: 3 ms or 10 ms Maximum
– 1 to 64-byte Page Write Operation
Low Power Dissipation
– 80 mA Active Current
– 3 mA Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Full Military and Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Option
256K (32K x 8)
High-speed
Parallel
EEPROM
AT28HC256
1. Description
The AT28HC256 is a high-performance electrically erasable and programmable read-
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256 offers
access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256
is deselected, the standby current is less than 5 mA.
The AT28HC256 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64
bytes of data are internally latched, freeing the addresses and data bus for other oper-
ations. Following the initiation of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a write cycle can be detected
by DATA Polling of I/O7. Once the end of a write cycle has been detected a new
access for a read or write can begin.
Atmel’s 28HC256 has additional features to ensure high quality and manufacturability.
The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.
0007N–PEEPR–9/09




AT28HC256 pdf, 반도체, 판매, 대치품
4.5 Toggle Bit
In addition to DATA Polling the AT28HC256 provides another method for determining the end
of a write cycle. During the write operation, successive attempts to read data from the device
will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop
toggling and valid data will be read. Testing the toggle bit may begin at any time during the
write cycle.
4.6 Data Protection
If precautions are not taken, inadvertent writes to any 5-volt-only nonvolatile memory may
occur during transition of the host system power supply. Atmel® has incorporated both hard-
ware and software features that will protect the memory against inadvertent writes.
4.6.1
Hardware Protection
Hardware features protect against inadvertent writes to the AT28HC256 in the following ways:
(a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on
delay – once VCC has reached 3.8V the device will automatically time out 5 ms typical) before
allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write
cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not
initiate a write cycle.
4.6.2
Software Data Protection
A software controlled data protection feature has been implemented on the AT28HC256.
When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP
feature may be enabled or disabled by the user; the AT28HC256 is shipped from Atmel with
SDP disabled.
SDP is enabled by the host system issuing a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to “Software Data Protection” algo-
rithm). After writing the 3-byte command sequence and after tWC the entire AT28HC256 will be
protected against inadvertent write operations. It should be noted, that once protected the host
may still perform a byte or page write to the AT28HC256. This is done by preceding the data to
be written by the same 3-byte command sequence.
Once set, SDP will remain active unless the disable command sequence is issued. Power
transitions do not disable SDP and SDP will protect the AT28HC256 during power-up and
power-down conditions. All command sequences must conform to the page write timing spec-
ifications. It should also be noted that the data in the enable and disable command sequences
is not written to the device and the memory addresses used in the sequence may be written
with data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the three byte command
sequence will start the internal write timers. No data will be written to the device; however, for
the duration of tWC, read operations will effectively be polling operations.
4.7 Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes
may be written to or read from in the same manner as the regular memory array.
4.8 Optional Chip Erase Mode
The entire device can be erased using a 6-byte software code. Please see “Software Chip
Erase” application note for details.
4 AT28HC256
0007N–PEEPR–9/09

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AT28HC256 전자부품, 판매, 대치품
11. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
12. Output Test Load
AT28HC256
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
CIN
COUT
Note:
46
8 12
1. This parameter is characterized and is not 100% tested.
Units
pF
pF
Conditions
VIN = 0V
VOUT = 0V
0007N–PEEPR–9/09
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