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PDF AM29PLI60C Data sheet ( Hoja de datos )
| Número de pieza | AM29PLI60C | |
| Descripción | 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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Am29PL160C
Data Sheet
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Publication Number 22143 Revision C Amendment +4 Issue Date June 12, 2002
1 page  
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
Regulated Voltage Range: VCC =3.0–3.6 V
Full Voltage Range: VCC = 2.7–3.6 V
Max access time, ns (tACC)
Max CE# access time, ns (tCE)
Max page access time, ns (tPACC)
Max OE# access time, ns (tOE)
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
-65R
65
65
25
25
VCC
VSS
Erase Voltage
Generator
Am29PL160C
-70R
-90
70 90
70 90
25 30
25 30
-120
120
120
30
30
DQ0–DQ15
Input/Output
Buffers
WE#
BYTE#
CE#
OE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
VCC Detector
A0–A19
A-1
Timer
STB
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
4
Am29PL160C
June 12, 2002
5 Page 
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes
or words. Refer to “Word/Byte Configuration” for
more information.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 4 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has de-
tails on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and
ICC read specifications apply. Refer to “Write Opera-
tion Status” for more information, and to “AC
Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# pin is both held at VCC ± 0.3 V. (Note that this is a
more restricted voltage range than VIH.) If CE# is held
at VIH, but not within VCC ± 0.3 V, the device will be in
the standby mode, but the standby current will be
greater. The device requires standard access time
(tCE) for read access when the device is in either of
these standby modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables this
mode when addresses remain stable for tACC + 30 ns.
The automatic sleep mode is independent of the CE#,
WE#, and OE# control signals. Standard address access
timings provide new data when addresses are changed.
While in sleep mode, output data is latched and always
available to the system. Note that during Automatic Sleep
mode, OE# must be at VIH before the device reduces
current to the stated sleep mode specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
10
Am29PL160C
June 12, 2002
11 Page | ||
| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet AM29PLI60C.PDF ] | |
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