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PDF AM50DLI28BG Data sheet ( Hoja de datos )
| Número de pieza | AM50DLI28BG | |
| Descripción | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM | |
| Fabricantes | Advanced Micro Devices | |
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Am50DL128BG
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 26089 Revision A Amendment +3 Issue Date January 8, 2002
1 page  
PRELIMINARY
Flash Erase And Programming Performance . . . 59
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 59
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 59
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 59
pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 60
pSRAM Power on and Deep Power Down . . . . . 60
Figure 34. Deep Power-down Timing.............................................. 60
Figure 35. Power-on Timing............................................................ 60
pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 61
Figure 36. Read Address Skew ..................................................... 61
Figure 37. Write Address Skew...................................................... 61
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 62
FTA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 62
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63
4
Am50DL128BG
January 8, 2003
5 Page 
PRELIMINARY
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the result-
ing output. The following subsections describe each of
these operations in further detail.
10
Am50DL128BG
January 8, 2003
11 Page | ||
| Páginas | Total 64 Páginas | |
| PDF Descargar | [ Datasheet AM50DLI28BG.PDF ] | |
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| Número de pieza | Descripción | Fabricantes |
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