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PDF Am53CF94KC Data sheet ( Hoja de datos )
| Número de pieza | Am53CF94KC | |
| Descripción | Enhanced SCSI-2 Controller (ESC) | |
| Fabricantes | Advanced Micro Devices | |
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PRELIMINARY
Am53CF94/Am53CF96
Enhanced SCSI-2 Controller (ESC)
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s Pin/function compatible with Emulex
FAS216/236
s AMD’s Patented programmable GLITCH
EATERTM Circuitry on REQ and ACK inputs
s 10 Mbytes/s synchronous Fast SCSI transfer
rate
s 20 Mbytes/s DMA transfer rate
s 16-Bit DMA interface plus 2 bits of parity
s Flexible three bus architecture
s Single-ended SCSI bus supported by
Am53CF94
s Differential SCSI bus supported by Am53CF96
s Selection of multiplexed or non-multiplexed
address and data bus
s High current drivers (48 mA) for direct
connection to the single-ended SCSI bus
s Supports Disconnect and Reselect commands
s Supports burst mode DMA operation with a
threshold of eight
s Supports 3-byte tagged-queueing as per the
SCSI-2 specification
s Supports group 2 and 5 command recognition
as per the SCSI-2 specification
s Advanced CMOS process for lower power
consumption
GENERAL DESCRIPTION
The Enhanced SCSI-2 Controller (ESC) was designed
to support Fast SCSI-2 transfer rates of up to
10 Mbytes/s in synchronous mode and up to 7 Mbytes/s
in the asynchronous mode. The ESC is downward com-
patible with the Am53C94/96, combining its functionality
with features such as Fast SCSI, programmable Active
Negation, a 24-bit transfer counter, and a part-unique ID
code containing manufacturer and serial # information.
AMD’s proprietary features such as power-down mode
for SCSI transceivers, programmable GLITCH EATER,
and extended Target command set are also included for
improved product performance.
The Enhanced SCSI-2 Controller (ESC) has a flexible
three bus architecture. The ESC has a 16-bit DMA inter-
face, an 8-bit host data interface and an 8-bit SCSI data
interface. The ESC is designed to minimize host inter-
vention by implementing common SCSI sequences in
hardware. An on-chip state machine reduces protocol
overheads by performing the required sequences in re-
sponse to a single command from the host. Selection,
s AMD’s exclusive programmable power-down
feature
s 24-Bit extended transfer counter allows for
data block transfer of up to 16 Mbytes
s Independently programmable 3-byte message
and group 2 identification
s Additional check for ID message during
bus-initiated Select with ATN
s Reselection has QTAG features of ATN3
s Access FIFO Command
s Delayed enable signal for differential drivers
avoid contention on SCSI differential lines
s Programmable Active Negation on REQ, ACK
and Data lines
s Register programmable control of assertion/
deassertion delay for REQ and ACK lines
s Part-unique ID code
s Am53CF94 available in 84-pin PLCC package
s Am53CF96 available in 100-pin PQFP package
s Am53CF94 available in 3.3 V version
s Supports clock operating frequencies from
10 MHz–40 MHz
s Supports Scatter-Gather or Back-to-Back
synchronous data transfers
reselection, information transfer and disconnection
commands are directly supported.
The 16-byte-internal FIFO further assists in minimizing
host involvement. The FIFO provides a temporary stor-
age for all command, data, status and message bytes as
they are transferred between the 16-bit host data bus
and the 8-bit SCSI data bus. During DMA operations the
FIFO acts as a buffer to allow greater latency in the DMA
channel. This permits the DMA channel to be sus-
pended for higher priority operations such as DRAM re-
fresh or reception of an ISDN packet.
Parity on the DMA bus is optional. Parity can either be
generated and checked or it can be simply passed
through.
The Target command set for the Am53CF94/96 in-
cludes an additional command, the Access FIFO com-
mand, to allow the host or DMA controller to remove re-
maining FIFO data following the host’s issuance of a
Target abort DMA command or following an abort due to
This document contains information on a product under development at Advanced Micro Devices Inc. The information is intended Publication# 17348 Rev. B Amendment /0
to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Issue Date: May 1993
1 page  
BLOCK DIAGRAM
PRELIMINARY
DMA 15-0
DMAP1-0
DMA Control
4
AD 7-0
Host Control
CS
BUSMD1-0
DFMODE
CLK
RESET
6
18 16 x 9 FIFO
(including parity)
8
18
Parity Logic
8
8
Register
Bank
Main
Sequencer
SCSI
Sequencer
AMD
9
SCSI Bus
Data + Parity
(Single Ended)
9
SCSI Bus
Data + Parity
Direction Control
9 SCSI Control
7 SCSI Control
Direction Control
17348B-7
Am53CF94/Am53CF96
5
5 Page 
PRELIMINARY
TSEL
MSG
TSEL
C/D
TSEL
I/O
– MSG
+ MSG
– C/D
+ C/D
– I/O
+ I/O
75ALS170
ISEL
ATN
– ATN
+ ATN
SDC 0
SD 0
SDC 1
SD 1
SDC 2
SD 2
– SD 0
+ SD 0
– SD 1
+ SD 1
– SD 2
+ SD 2
75ALS170
75ALS170
Vcc
SELC
GND
SEL
BSYC
GND
BSY
RSTC
GND
RST
GND
Vcc
TSEL
REQC
REQ
ISEL
ACKC
ACK
75ALS171
– SEL
+ SEL
– BSY
+ BSY
– RST
+ RST
– REQ
+ REQ
– ACK
+ ACK
SDC 3
SD 3
SDC 4
SD 4
SDC 5
SD 5
– SD 3
+ SD 3
– SD 4
+ SD 4
– SD 5
+ SD 5
75ALS170
SDC 6
SD 6
SDC 7
SD 7
SDC P
SD P
– SD 6
+ SD 6
– SD 7
+ SD 7
– SD P
+ SD P
75ALS170
AMD
GND
75ALS171
17348B-14
Differential Transceiver Connections for the Differential SCSI Bus Configuration
Using 75ALS170 and 75ALS171 Transceivers
Am53CF94/Am53CF96
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet Am53CF94KC.PDF ] | |
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