PDF AM79C981 Data sheet ( Hoja de datos )

Número de pieza	AM79C981
Descripción	Integrated Multiport Repeater Plus (IMR+)
Fabricantes	Advanced Micro Devices
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PRELIMINARY Am79C981 Integrated Multiport Repeater Plus™ (IMR+™) DISTINCTIVE CHARACTERISTICS s Enhanced version of AMD’s Am79C980 Integrated Multiport Repeater™ (IMR™) chip with the following enhancements: — Additional management port features — Minimum mode provides support for an extra four LED outputs per port for additional status in non-intelligent repeater designs — Pin/socket-compatible with the Am79C980 IMR chip — Fully backward-compatible with existing IMR device designs s Interfaces directly with the Am79C987 HIMIB™ device to build a fully managed multiport repeater s CMOS device features high integration and low power with a single +5 V supply s Repeater functions comply with IEEE 802.3 Repeater Unit speciﬁcations s Eight integral 10BASE-T transceivers utilize the required predistortion transmission technique s Attachment unit interface (AUI) port allows connectivity with 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet) networks, as well as 10BASE-F and/or Fiber Optic Inter-Repeater Link (FOIRL) segments s On-board PLL, Manchester encoder/decoder, and FIFO s Expandable to increase number of repeater ports s All ports can be separately isolated (partitioned) in response to excessive collision conditions or fault conditions s Network management and optional features are accessible through a dedicated serial management port s Twisted-pair Link Test capability conforming to the 10BASE-T standard. The receive Link Test function can be optionally disabled through the management port to facilitate interoperability with devices that do not implement the Link Test function s Programmable option of Automatic Polarity Detection and Correction permits automatic recovery due to wiring errors s Full amplitude and timing regeneration for retransmitted waveforms s Preamble loss effects eliminated by deep FIFO GENERAL DESCRIPTION The Integrated Multiport Repeater Plus (IMR+) chip is a VLSI circuit that provides a system-level solution to de- signing a compliant 802.3 repeater incorporating 10BASE-T transceivers. The device integrates the Repeater functions speciﬁed by Section 9 of the IEEE 802.3 standard and Twisted-Pair Transceiver functions complying with the 10BASE-T standard. The Am79C981 provides eight integral twisted-pair medium attachment units (MAUs) and an attachment unit interface (AUI) port in an 84-pin plastic leaded chip carrier (PLCC). A network based on the 10BASE-T standard uses un- shielded twisted-pair cables, thereby providing an eco- nomical solution to networking by allowing the use of low-cost unshielded twisted-pair (UTP) cable or existing telephone wiring. The total number of ports per repeater unit can be in- creased by connecting multiple IMR+ devices through their expansion ports, minimizing the total cost per re- peater port. Furthermore, a general-purpose attach- ment unit interface (AUI) provides connection capability to 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet) coaxial networks, as well as 10BASE-F and/or Fiber Optic Inter-Repeater Link (FOIRL) ﬁber segments. Net- work management and test functions are provided through TTL-compatible I/O pins. The IMR+ device interfaces directly with AMD’s Am79C987 Hardware Implemented Management In- formation Base™ (HIMIB) chip to build a fully managed multiport repeater as speciﬁed by the IEEE 802.3 (Layer Management for 10 Mb/s Baseband Repeaters) standard. When the IMR+ and HIMIB devices are interconnected, complete repeater and per-port statis- tics are maintained and can be accessed on demand using a simple 8-bit parallel interface. Publication# 17306 Rev: B Amendment/0 Issue Date: January 1999 This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. 1-71 1 page PRELIMINARY ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. Am79C981 JC OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial (0°C to +70°C) PACKAGE TYPE J = 84-Pin Plastic Leaded Chip Carrier (PL 084) SPEED Not Applicable DEVICE NUMBER/DESCRIPTION Am79C981 Integrated Multiport Repeater Plus (IMR+) Valid Combinations Am79C981 JC Valid Combinations Valid combinations list conﬁgurations planned to be sup- ported in volume for this device. Consult the local AMD sales ofﬁce to conﬁrm availability of speciﬁc valid combinations and to check on newly released combinations. Am79C981 1–75 5 Page PRELIMINARY AMD Expansion Port The IMR+ chip Expansion Port is comprised of five pins; two are bi-directional signals (DAT and JAM), two are in- put signals (ACK and COL), and one is an output signal (REQ). These signals are used when a multiple-IMR+ device repeater application is employed. In this configu- ration, all IMR+ chips must be clocked synchronously with a common clock connected to the X1 inputs of all IMR+ devices. Reset needs to be synchronized to X1 clock. The IMR+ device expansion scheme allows the use of multiple IMR+ chips in a single board repeater or a modular multiport repeater with a backplane architec- ture. The DAT pin is a bidirectional I/O pin which can be used to transfer data between the IMR+ devices in a multiple-IMR+ chip design. The data sent over the DAT line is in NRZ format and is synchronized to the common clock. The JAM pin is another bidirectional I/O pin that is used by the active IMR+ chip to communicate its internal status to the remaining (inactive) IMR+ devices. When JAM is asserted HIGH, it indicates that the active IMR+ device has detected a collision condition and is generat- ing Jam Sequence. During this time when JAM is as- serted HIGH, the DAT line is used to indicate whether the active IMR+ chip is detecting collision on one port only or on more than one port. When DAT is driven HIGH by the IMR+ chip (while JAM is asserted by the IMR+ chip), then the active IMR+ device is detecting a collision condition on one port only. This ‘one-port-left’ signaling is necessary for a multiple-IMR+ device re- peater to function correctly as a single multiport repeater unit. The IMR+ chip also signals the ‘one port left’ colli- sion condition in the event of a runt packet or collision fragment; this signal will continue for one expansion port bus cycle (100 ns) before deasserting REQ. The arbitration for access to the bussed bi-directional signals (DAT and JAM) is provided by one output (REQ) and two inputs (ACK and COL). The IMR+ chip asserts the REQ pin to indicate that it is active and wishes to drive the DAT and JAM pins. An external arbiter senses the REQ lines from all the IMR+ devices and asserts the ACK line when one and only one IMR+ chip is asserting its REQ line. If more than one IMR+ chip is asserting its REQ line, the arbiter must assert the COL signal, indi- cating that more than one IMR+ device is active. More than one active IMR+ device at a time constitutes a colli- sion condition, and all IMR+ devices are notified of this occurence via the COL line of the Expansion Port. Note that a transition from multiple IMR+ devices arbi- trating for the DAT and JAM pins (with COL asserted, ACK deasserted) to a condition when only one IMR+ chip is arbitrating for the DAT and JAM pins (with ACK asserted, COL deasserted) involves one expansion port bus cycle (100 ns). During this transitional bus cycle, COL is deasserted, ACK is asserted, and the DAT and JAM pins are not driven. However, each IMR+ device will remain in the collision state (transmitting jam se- quence) during this transitional bus cycle. In subse- quent expansion port bus cycles (REQ and ACK still asserted), the IMR+ devices will return to the ‘master and slaves’ condition where only one IMR+ device is ac- tive (with collision) and is driving the DAT and JAM pins. An understanding of this sequence is crucial if non- IMR+ devices (such as an Ethernet controller) are con- nected to the expansion bus. Specifically, the last device to back off of the Expansion Port after a multi- IMR+ chip collision must assert the JAM line until it too drops its request for the Expansion Port. External Arbiter A simple arbitration scheme is required when multiple IMR+ devices are connected together to increase the to- tal number of repeater ports. The arbiter should have one input (REQ1...REQn) for each of the n IMR+ de- vices to be used, and two global outputs (COL and ACK). This function is easily implemented in a PAL® de- vice, with the following logic equations: ACK = + REQ1 & REQ2 & REQ3 & ....REQn REQ1 & REQ2 & REQ3 & ....REQn • • • + REQ1 & REQ2 & REQ3 & .... REQn COL = ACK & (REQ1 + REQ2 + REQ3 + ... REQn) Above equations are in positive logic, i.e., a variable is true when asserted. A single PALCE16V8 will perform the arbitration func- tion for a repeater based on several IMR+ devices. Am79C981 1–81 11 Page

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