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PDF AM8530 Data sheet ( Hoja de datos )
| Número de pieza | AM8530 | |
| Descripción | Serial Communications Controller | |
| Fabricantes | Advanced Micro Devices | |
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Am8530H/Am85C30
Serial Communications Controller
1992 Technical Manual
ADV A N C E D M I C R O D E V I C E S
1 page  
Table of Contents
Chapter 4
AMD
3.9 Block Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3.9.1 Wait on Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
3.9.2 Wait on Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
3.9.3 DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
3.9.3.1 DMA Request on Transmit
(using W/REQ) . . . . . . . . . . . . . . . . . . . . . . 3–17
3.9.3.2 DMA Request on Transmit
(using DTR/REQ) . . . . . . . . . . . . . . . . . . . . 3–18
3.9.3.3 DTR/REQ Deactivation Timing . . . . . . . . . . 3–19
3.9.3.4 DMA Request on Receive (using W/REQ) . 3–20
Data Communication Modes Functional Description
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4.2 Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4.2.1 Asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4.2.2 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . 4–4
4.2.2.1 Synchronous Character-Oriented
Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
4.2.2.2 Synchronous Bit-Oriented . . . . . . . . . . . . . . 4–4
4.3 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
4.4 Receiver Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
4.4.1 Rx Character Length . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
4.4.2 Rx Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4.4.3 Rx Modem Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.5 Transmitter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.5.1 Tx Character Length . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.5.2 Tx Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.5.3 Break Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.5.4 Transmit Modem Control . . . . . . . . . . . . . . . . . . . . . . 4–11
4.5.5 Auto RTS Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.6 Asynchronous Mode Operation . . . . . . . . . . . . . . . . . . . . . . . 4–12
4.6.1 Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
4.6.1.1 Receiver Initialization . . . . . . . . . . . . . . . . . 4–12
4.6.1.2 Framing Error . . . . . . . . . . . . . . . . . . . . . . . 4–12
4.6.1.3 Break Detection . . . . . . . . . . . . . . . . . . . . . . 4–13
4.6.1.4 Clock Selection . . . . . . . . . . . . . . . . . . . . . . 4–13
4.6.2 Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . 4–13
4.6.2.1 Transmitter Initialization . . . . . . . . . . . . . . . 4–13
4.6.2.2 Stop Bit Selection . . . . . . . . . . . . . . . . . . . . 4–13
4.7 SDLC Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
4.7.1 Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
4.7.1.1 Flag Detect Output . . . . . . . . . . . . . . . . . . . 4–14
4.7.1.2 Receiver Initialization . . . . . . . . . . . . . . . . . 4–14
4.7.1.3 10x19-Bit Frame Status FIFO . . . . . . . . . . . 4–14
4.7.1.3.1 FIFO Enabling/Disabling . . . . . . . . 4–15
4.7.1.3.2 FIFO Read Operation . . . . . . . . . . 4–15
4.7.1.3.3 FIFO Write Operation . . . . . . . . . . 4–15
4.7.1.3.4 14-Bit Byte Counter . . . . . . . . . . . 4–15
4.7.1.3.5 Am85C30 Frame Status
FIFO Operation Clarification . . . . . 4–18
4.7.1.3.6 Am85C30 Aborted Frame
Handling When Using the 10x19
Frame Status FIFO . . . . . . . . . . . . 4–19
4.7.1.4 Address Search Mode . . . . . . . . . . . . . . . . . 4–19
4.7.1.5 Abort Detection . . . . . . . . . . . . . . . . . . . . . . 4–20
4.7.1.6 Residue Bits . . . . . . . . . . . . . . . . . . . . . . . . 4–21
4.7.2 SDLC Mode CRC Polynomial Selection . . . . . . . . . . 4–21
4.7.2.1 Rx CRC Initialization . . . . . . . . . . . . . . . . . . 4–22
4.7.2.2 Rx CRC Enabling . . . . . . . . . . . . . . . . . . . . 4–22
5 Page 
CHAPTER 1
General Information
1.1 INTRODUCTION
The Am85C30 and Am8530H SCCs (Serial Communications Controller) are dual chan-
nel, multiprotocol data communications peripherals designed for use with 8- and 16-bit
microprocessors. The SCC functions as a serial-to-parallel, parallel-to-serial converter/
controller. The SCC can be software configured to satisfy a wide variety of serial commu-
nications applications, including: Bus Architectures (full- and half-duplex), Token Passing
Ring (SDLC Loop mode), and Star configurations (similar to SLAN).
The SCC contains a variety of internal functions including on-chip baud rate generators,
digital phase-lock loops, and crystal oscillators, which dramatically reduce the need for
external logic. In addition, SDLC/HDLC enhancements have been added to the Am85C30
that allow it to be used more effectively in high speed applications.
The SCC handles asynchronous formats, synchronous character-oriented protocols such
as IBM BISYNC, and Synchronous bit-oriented protocols such HDLC and IBM SDLC.
This versatile device supports virtually any serial data transfer application (telecommuni-
cations, cassette, diskette, tape drivers, etc.).
The device can generate and check CRC codes in any Synchronous mode. The SCC
also has facilities for Modem controls in both channels. In applications where these con-
trols are not needed, the Modem controls can be used for general purpose I/O.
With access to the Write registers and Read registers in each channel, the user can con-
figure the SCC so that it can handle all asynchronous formats regardless of data size,
number of stop bits, or parity requirements. The SCC also accommodates all synchro-
nous formats including character, byte, and bit-oriented protocols.
Within each operating mode, the SCC also allows for protocol variations by handling odd
or even parity bits, character insertion or deletion, CRC generation and checking, break/
abort generation and detection, and many other protocol-dependent features.
Unless otherwise stated, the functional description in this Technical Manual applies to
both the NMOS Am8530H and CMOS Am85C30. When the enhancements in the
Am85C30 are disabled, it is completely downward compatible with the Am8530H.
1.2 CAPABILITIES
s Two independent full-duplex channels
s Synchronous data rates:
– Up to 1/4 of the PCLK (i.e., 4 Mbit/sec. maximum data rate with 16 MHz PCLK
Am85C30)
– Up to 1Mbit/second with a 16 MHz clock rate (FM encoding using DPLL in
Am85C30)
– Up to 500 Kbit/second with 16 MHz clock rate (NRZI encoding using DPLL in
Am85C30)
1–3
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet AM8530.PDF ] | |
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