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PDF LTC1456I Data sheet ( Hoja de datos )
| Número de pieza | LTC1456I | |
| Descripción | 12-Bit Rail-to-Rail Micropower DAC with Clear Input | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC1456I (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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FEATURES
s SO-8 Package
s 12-Bit Resolution
s Buffered True Rail-to-Rail Voltage Output
s Asynchronous Clear Input
s Built-In Reference
s Schmitt Trigger On Clock Input Allows Direct
Optocoupler Interface
s Power-On Reset Clears DAC to 0V
s 3-Wire Cascadable Serial Interface
s Maximum DNL Error: 0.5LSB
s Low Cost
U
APPLICATIONS
s Digital Calibration
s Industrial Process Control
s Automatic Test Equipment
s Cellular Telephones
LTC1456
12-Bit Rail-to-Rail
Micropower DAC
with Clear Input
DESCRIPTION
The LTC®1456 is a complete single supply, rail-to-rail
voltage output, 12-bit digital-to-analog converter (DAC) in
an SO-8 package. It includes a rail-to-rail output buffer
amplifier and an easy-to-use 3-wire cascadable serial
interface. The LTC1456 includes a CLR pin that asynchro-
nously clears the DAC to zero scale.
The LTC1456 has an internal 2.048V reference and a full-
scale output of 4.095V. It operates on a 4.5V to 5.5V
supply, dissipating 2.2mW.
The low power supply current and the space saving SO-8
package make the LTC1456 ideal for battery-powered
applications.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
µP
TO
OTHER
DACS
Functional Block Diagram: 12-Bit Rail-to-Rail DAC with Clear Input
2 DIN
4.5V TO 5.5V
8
VCC 2.048V
1 CLK
3 CS/LD
12-BIT
SHIFT
REG
AND
DAC
LATCH
12-BIT
DAC
4 DOUT
6 CLR POWER-ON
RESET
GND
5
+ VOUT 7 RAIL-TO-RAIL
VOLTAGE
– OUTPUT
1456 TA01
Differential Nonlinearity
vs Input Code
0.5
0
–0.5
0 512 1024 1536 2048 2560 3072 3584 4095
CODE
1456 TA02
1
1 page  
LTC1456
PIN FUNCTIONS
CLK (Pin 1): The Serial Interface Clock. Internal Schmitt
trigger on this input allows direct optocoupler interface.
DIN (Pin 2): The Serial Interface Data. Data on the DIN pin
is latched into the shift register on the rising edge of the
serial clock.
CS/LD (Pin 3): The Serial Interface Enable and Load
Control. When CS/LD is low the CLK signal is enabled, so
the data can be clocked in. When CS/LD is pulled high,
data is loaded from the shift register into the DAC
register, updating the DAC output. When CS/LD is high
the CLK is disabled internally.
DOUT (Pin 4): The Output of the Shift Register Which
Becomes Valid on the Rising Edge of the Serial Clock.
GND (Pin 5): Ground.
CLR (Pin 6): The Clear Input. When pulled low, this pin
asynchronously clears the internal shift and DAC registers
to zero scale. Should be tied high for normal operation.
VOUT (Pin 7): The Buffered DAC Output.
VCC (Pin 8): The Positive Supply Input. 4.5V ≤ VCC ≤ 5.5V.
Requires a bypass capacitor to ground.
BLOCK DIAGRA
CLK 1
2.048V
8 VCC
DIN 2
CS/LD 3
12-BIT
SHIFT
REGISTER
LD
DAC
REGISTER
12-BIT
DAC
+
7 VOUT
–
DOUT 4
WU W
TI I G DIAGRA
CLK
t9
DIN
B0
PREVIOUS WORD
CS/LD
POWER-ON
RESET
t1 t2
B11
MSB
t4
B10
t8
6 CLR
5 GND
1146 BD
t6 t7
t3
B1 B0
LSB
t5
DOUT
B11
PREVIOUS WORD
B10
B11
B1 B0 CURRENT WORD
1456 TD
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet LTC1456I.PDF ] | |
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