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LTC1662CMS8 데이터시트 PDF




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부품번호 LTC1662CMS8 기능
기능 Ultralow Power/ Dual 10-Bit DAC in MSOP
제조업체 Linear Technology
로고 Linear Technology 로고


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LTC1662CMS8 데이터시트, 핀배열, 회로
FEATURES
s Ultralow Power: 1.5µA (Typ) ICC per DAC Plus
0.05µA Sleep Mode for Extended Battery Life
s Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Size of an SO-8
s Wide 2.7V to 5.5V Supply Range
s Double Buffered for Simultaneous DAC Updates
s Rail-to-Rail Voltage Outputs Drive 1000pF
s Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
s Reference Input Impedance Is Code-Independent
(7.1MTyp)—Eliminates External Buffers
s 3-Wire Serial Interface with
Schmitt Trigger Inputs
s Differential Nonlinearity: ±0.75LSB Max
U
APPLICATIO S
s Mobile Communications
s Portable Battery-Powered Instruments
s Remote Industrial Devices
s Digitally Controlled Amplifiers and Attenuators
s Automatic Calibration for Manufacturing
Final Electrical Specifications
LTC1662
Ultralow Power, Dual
10-Bit DAC in MSOP
DESCRIPTIO
March 2000
The LTC®1662 is an ultralow power, fully buffered volt-
age output, dual 10-bit digital-to-analog converter (DAC).
Each DAC draws just 1.7µA (typ) total supply-plus-
reference operating current, yet is capable of supplying
DC output currents in excess of 1mA and reliably driving
capacitive loads of up to 1000pF. A programmable Sleep
mode further reduces total operating current to a negli-
gible 0.05µA.
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent lin-
earity while allowing for an exceptionally small external
form factor. The double-buffered input logic provides
simultaneous update capability and can be used to write to
either DAC without interrupting Sleep mode.
With its ultralow operating current and exceptionally
small size, the LTC1662 is ideal for use in battery-
powered products.
The LTC1662 is pin- and software-compatible with the
LTC1661 micropower dual 10-bit DAC. It is available in
8-pin MSOP and PDIP packages and is specified over the
industrial temperature range.
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
VOUT A
8
GND
7
10-BIT
DAC A
VCC VOUT B
65
10-BIT
DAC B
1
CS/LD
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
23
SCK DIN
4
REF
1662 BD
Total Supply-Plus-Reference
Operating Current
5.5
VREF = VCC
5.0 TA = 25°C
4.5 CODE = 1023
4.0
CODE = 512
3.5
CODE = 0
3.0
2.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCC (V)
1662 G01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1




LTC1662CMS8 pdf, 반도체, 판매, 대치품
LTC1662
WU
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C.
The q denotes the specifications which apply over the full operating temperature
SYMBOL
t5
t6
t7
t9
t11
PARAMETER
CS/LD Pulse Width
LSB SCK High to CS/LD High
CS/LD Low to SCK High
SCK Low to CS/LD Low
CS/LD High to SCK Positive Edge
SCK Frequency
CONDITIONS
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
Square Wave (Note 6)
MIN
q 150
q 50
q 30
q0
q 30
q
TYP MAX UNITS
30 ns
3 ns
– 14 ns
– 5 ns
0 ns
10 MHz
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined and tested at VCC = 5V,
VREF = 4.096V, from code 20 to code 1023. See Figure 2.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kin parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS; i.e.,
codes k = 102 and k = 922.
Note 6: Guaranteed by design, not subject to test.
Note 7: One DAC output loaded.
WU W
TI I G DIAGRA
SCK
DIN
CS/LD
t1
t2
t3 t4
t6
t9 t11
A3 A2 A1 X1 X0
t5 t7
1662 TD
TYPICAL PERFOR A CE CHARACTERISTICS
4
Integral Nonlinearity (INL)
4
3
2
1
0
–1
–2
–3
–4
0
256 512 768 1023
CODE
1662 G02
Differential Nonlinearity (DNL)
0.75
0.60
0.40
0.20
0
–0.20
–0.40
–0.60
– 0.80
0
256 512 768 1023
CODE
1662 G03

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LTC1662CMS8 전자부품, 판매, 대치품
U
OPERATIO
Transfer Function
The transfer function for the LTC1662 is:
VOUT(IDEAL)
=

k
1024
VREF
where k is the decimal equivalent of the binary DAC input
code D9-D0 and VREF is the voltage at REF (Pin 6).
Power-On Reset
The LTC1662 positively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) should be kept within the range
–0.3V VREF VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken during power
supply turn-on and turn-off sequences, when the voltage
at VCC (Pin 6) is in transition.
Serial Interface
See Table 1. The 16-bit Input word consists of the 4-bit
Control code, the 10-bit Input code and two don’t-care bits.
Table 1. LTC1662 Input Word
Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
Control Code
Input Code
Don’t
Care
AftertheInputwordisloadedintotheregister(seeFigure␣ 1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide Input code data path is then buffered
by two latch registers.
The first of these, the Input Register, is used for loading new
input codes. The second buffer, the DAC Register, is used
for updating the DAC outputs. Each DAC has its own 10-bit
Input Register and 10-bit DAC Register.
By selecting the appropriate 4-bit Control code (see Table␣ 2)
it is possible to perform single operations, such as loading
one DAC or changing Power-Down status (Sleep/Wake).
LTC1662
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part up.
The DACs can be loaded separately or together, but the
outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the DIN input
is shifted into the 16-bit Shift Register on the positive edge
of SCK. The 4-bit Control code, A3-A0, is loaded first, then
the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last.
When the full 16-bit Input word has been shifted in, CS/LD
is pulled high, causing the system to respond according to
Table␣ 2. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
DAC control code 1110b is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital circuits
remain active while the analog sections are disabled; static
power consumption is greatly reduced. The reference
input and analog outputs are set in a high impedance state
and all DAC settings are retained in memory so that when
Sleep mode is exited, the outputs of DACs not updated by
the Wake command are restored to their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110b (the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared with
new input codes during Sleep (control codes 0001b and
0010b); then, a single command (1000b) can be used both
to wake the part and to update the output values.
Alternatively, one DAC may be loaded with a new input
code during Sleep; then with just one command, the other
DAC is loaded, the part is awakened and both outputs are
updated.
For example, control code 0001b is used to load DAC A
during Sleep. Then Control code 0101b loads DAC B,
wakes the part and simultaneously updates both DAC
outputs.
7

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부품번호상세설명 및 기능제조사
LTC1662CMS8

Ultralow Power/ Dual 10-Bit DAC in MSOP

Linear Technology
Linear Technology

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