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PDF LTC1663 Data sheet ( Hoja de datos )
| Número de pieza | LTC1663 | |
| Descripción | 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC1663 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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LTC1663
10-Bit Rail-to-Rail
Micropower DAC with 2-Wire Interface
FEATURES
s Micropower 10-Bit DAC in SOT-23
s Low Operating Current: 60µA
s Ultralow Power Shutdown Mode: 10µA
s 2-Wire Serial Interface Compatible
with SMBus and I2CTM
s Single 2.7V to 5.5V Operation
s Selectable Internal Reference or Ratiometric to VCC
s Buffered True Rail-to-Rail Voltage Output
s Maximum DNL Error: 0.75LSB
s Power-On Reset
s 8 User Selectable Addresses (MSOP Package)
s 0.6V VIL and 1.4V VIH for SDA and SCL
s Small 5-Lead SOT-23 and 8-Lead MSOP Packages
U
APPLICATIO S
s Digital Calibration
s Offset/Gain Adjustment
s Industrial Process Control
s Automatic Test Equipment
s Arbitrary Function Generators
s Battery-Powered Data Conversion Products
DESCRIPTIO
The LTC®1663 is a 10-bit voltage output DAC with true
buffered rail-to-rail output voltage capability. It operates
from a single supply with a range of 2.7V to 5.5V. The
reference for the DAC is selectable between the supply
voltage or an internal bandgap reference. Selecting the
internal bandgap reference will set the full-scale output
voltage range to 2.5V. Selecting the supply as the refer-
ence sets the output voltage range to the supply voltage.
The part features a simple 2-wire serial interface compat-
ible with SMBus and I2C that allows communication
between many devices. The internal data registers are
double buffered to allow for simultaneous update of
several devices at once. The DAC can be put in low current
power-down mode for use in power conscious systems.
Power-on reset ensures the DAC output is at 0V when
power is initially applied, and all internal registers are
cleared.
, LTC and LT are registered trademarks of Linear Technology Corporation.
I2C is a trademark of Philips Electronics N.V.
BLOCK DIAGRA
1.25V
BANDGAP
REFERENCE
4 (5)
VCC
REFERENCE
SELECT
10-BIT
DAC LATCH
MSOP
PACKAGE
ONLY
(6) AD0
(2) AD1
(3) AD2
COMMAND
LATCH
INPUT
LATCH
2-WIRE INTERFACE
SDA
1 (1)
SCL
5 (4)
NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE
+
–
R
R
GND
2 (7)
VOUT 3 (8)
1663 BD
Differential Nonlinearity (DNL)
1.0
0.8
VREF = VCC = 5V
TA = 25°C
0.6
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
–1.0
0
28 156 384 512 640 768 896 1024
CODE
1663 G02
1
1 page  
LTC1663
PIN FUNCTIONS
SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged by
the SDA pin. High impedance pin while data is shifted in.
Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to VCC.
AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin. Data
is shifted into the SDA pin at the rising edges of the clock.
This high impedance pin requires a pull-up resistor or
current source to VCC.
VCC (Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ VCC
≤ 5.5V. Also used as the reference voltage input when the
part is programmed to use VCC as the reference.
AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
GND (Pin 7, Pin 2 on SOT-23): System Ground.
VOUT (Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered
rail-to-rail DAC output.
DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆VOUT – LSB)/LSB
Where ∆VOUT is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code that guarantees the output will be greater than
zero. The INL error at a given input code is calculated as
follows:
INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB
Where VOUT is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = VREF/1024
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
5
5 Page 
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
LTC1663
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.007
(0.18)
0° – 6° TYP
0.021 ± 0.006
(0.53 ± 0.015)
0.040 ± 0.006
(1.02 ± 0.15)
SEATING
PLANE
0.012
(0.30)
REF
0.0256
(0.65)
BSC
0.034 ± 0.004
(0.86 ± 0.102)
0.006 ± 0.004
(0.15 ± 0.102)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.118 ± 0.004*
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
8 76 5
0.118 ± 0.004**
(3.00 ± 0.102)
MSOP (MS8) 1098
1 234
S5 Package
5-Lead Plastic SOT-23
(LTC DWG # 05-08-1633)
2.80 – 3.00
(0.110 – 0.118)
(NOTE 3)
2.60 – 3.00
(0.102 – 0.118)
1.50 – 1.75
(0.059 – 0.069)
1.90
(0.074)
REF
0.00 – 0.15
(0.00 – 0.006)
0.95
(0.037)
REF
0.90 – 1.45
(0.035 – 0.057)
0.35 – 0.55
(0.014 – 0.022)
0.09 – 0.20
(0.004 – 0.008)
(NOTE 2)
0.35 – 0.50
0.90 – 1.30
(0.014 – 0.020) (0.035 – 0.051)
FIVE PLACES (NOTE 2)
S5 SOT-23 0599
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DIMENSIONS ARE INCLUSIVE OF PLATING
3. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
4. MOLD FLASH SHALL NOT EXCEED 0.254mm
5. PACKAGE EIAJ REFERENCE IS SC-74A (EIAJ)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LTC1663.PDF ] | |
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