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PDF LTC1664CGN Data sheet ( Hoja de datos )

Número de pieza LTC1664CGN
Descripción Micropower Quad 10-Bit DAC
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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No Preview Available ! LTC1664CGN Hoja de datos, Descripción, Manual

FEATURES
s Tiny: 4 DACs in the Board Space of an SO-8
s Micropower: 59µA per DAC Plus
1µA Sleep Mode for Extended Battery Life
s Wide 2.7V to 5.5V Supply Range
s Rail-to-Rail Voltage Outputs Drive 1000pF
s Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
s Reference Input Has Constant Impedance over All
Codes—Eliminates External Reference Buffer
s Individually Addressable DACs
s Differential Nonlinearity: ≤ ±0.75LSB Max
s Pin-Compatible Octal Version Available (LTC1660)
U
APPLICATIO S
s Mobile Communications
s Remote Industrial Devices
s Automatic Calibration for Manufacturing
s Portable Battery-Powered Instruments
s Trim/Adjust Applications
Final Electrical Specifications
LTC1664
Micropower Quad
10-Bit DAC
January 2000
DESCRIPTIO
The LTC®1664 integrates four accurate, serially addres-
sable 10-bit digital-to-analog converters (DACs) in a tiny
16-pin Narrow SSOP package. Each buffered DAC draws
just 59µA total supply current, yet is capable of supplying
DC output currents in excess of 5mA and reliably driving
capacitive loads of up to 1000pF. Sleep mode further
reduces total supply current to 1µA.
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent lin-
earity while allowing for an exceptionally small external
form factor.
Ultralow supply current, power-saving Sleep mode and
extremely compact size make the LTC1664 ideal for
battery-powered applications, while its ease of use, high
performance and wide supply range make it an excellent
choice as a general purpose converter.
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
GND 1
VOUT A 2
VOUT B 3
REF 6
CS/LD 7
SCK 8
10-BIT
DAC A
10-BIT
DAC B
10-BIT
DAC D
10-BIT
DAC C
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
16 VCC
5 VOUT D
4 VOUT C
11 CLR
10 DOUT
9 DIN
1664 BD
LTC1664 Differential Nonlinearity (DNL)
1
0.8
VCC = 5V
VREF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0 256
512
CODE
768 1023
1664 G08
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1664CGN pdf
LTC1664
TYPICAL PERFOR A CE CHARACTERISTICS
Midscale Output Voltage
vs Load Current
3 VREF = VCC
2.9 CODE = 512
2.8
2.7 VCC = 5.5V
2.6
2.5 VCC = 5V
2.4
2.3 VCC = 4.5V
2.2
2.1
2
SOURCE
SINK
–30 –20 –10 0 10
IOUT (mA)
20 30
1664 G01
Minimum VOUT vs
Load Current (Output Sinking)
1400
VCC = 5V
1200 CODE = 0
125°C
1000
800
25°C
600
–55°C
400
200
0
0 2 4 6 8 10
| |IOUT (mA) (Sinking)
1664 G04
Midscale Output Voltage
vs Load Current
2 VREF = VCC
1.9 CODE = 512
1.8
1.7 VCC = 3.6V
1.6
1.5 VCC = 3V
1.4
1.3 VCC = 2.7V
1.2
1.1
1 SOURCE SINK
–15 –12 – 8 – 4 0 4
IOUT (mA)
8
12 15
1664 G02
Large-Signal Step Response
5
VCC = VREF = 5V
10% TO
4 90% STEP
3
2
1
0
0 20 40 60 80 100
TIME (µs)
1664 G05
Load Regulation vs Output Current
2 VCC = VREF = 3V
CODE = 512
1.5
1
0.5
0
–0.5
–1
–1.5
–2
SOURCE
SINK
–500
0
IOUT (µA)
500
1664 G10
Minimum Supply Headroom vs
Load Current (Output Sourcing)
1400
1200
VREF = 4.096V
VOUT < 1LSB
CODE = 1023
1000
125°C
800
25°C
600
–55°C
400
200
0
0 2 4 6 8 10
| |IOUT (mA) (Sourcing)
1664 G03
Load Regulation vs Output Current
2 VCC = VREF = 5V
CODE = 512
1.5
1
0.5
0
–0.5
–1
–1.5
–2
SOURCE
SINK
–2 –1
0
1
IOUT (mA)
2
1664 G09
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LTC1664CGN arduino
U
OPERATIO
LTC1664
OUTPUT
VOLTAGE
VREF = VCC
VREF = VCC
INPUT CODE
(c)
POSITIVE
FSE
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
0 512 1023
INPUT CODE
(a)
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1665/60 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
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