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PDF LTC1771 Data sheet ( Hoja de datos )
| Número de pieza | LTC1771 | |
| Descripción | High Efficiency Step-Down DC/DC Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Very Low Standby Current: 10µA
s Available in Space-Saving 8-Lead MSOP Package
s Output Currents: Up to 5A
s Wide VIN Range: 2.8V to 20V Operation
s VOUT Range: 1.23V to 18V
s High Efficiency: Over 93% Possible
s ±2% Output Accuracy
s Very Low Dropout Operation: 100% Duty Cycle
s Current Mode Operation for Excellent Line and
Load Transient Response
s Defeatable Burst ModeTM Operation
s Short-Circuit Protected
s Optional Programmable Soft-Start
s Micropower Shutdown: IQ = 2µA
U
APPLICATIO S
s Cellular Telephones and Wireless Modems
s 1- to 4-Cell Lithium-Ion-Powered Applications
s Portable Instruments
s Battery-Powered Equipment
s Battery Chargers
s Scanners
LTC1771
10µA Quiescent Current
High Efficiency Step-Down
DC/DC Controller
DESCRIPTIO
The LTC®1771 is a high efficiency current mode step-
down DC/DC controller that draws as little as 10µA DC
supply current to regulate the output at no load while
maintaining high efficiency for loads up to several amps.
The LTC1771 drives an external P-channel power MOSFET
using a current mode, constant off-time architecture. An
external sense resistor is used to program the operating
current level. Current mode control provides short-circuit
protection, excellent transient response and controlled
start-up behavior. Burst Mode operation enables the
LTC1771 to maintain high efficiency down to extremely
low currents. Shutdown mode further reduces the supply
current to a mere 2µA. For low noise applications, Burst
Mode operation can be easily disabled with the MODE pin.
Wide input supply range of 2.8V to 18V (20V maximum)
and 100% duty cycle operation for low dropout make the
LTC1771 ideal for a wide variety of battery-powered appli-
cations where maximizing battery life is important.
The LTC1771’s availability in both 8-lead MSOP and SO
packages provides for a minimum area solution.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
VIN
4.5V TO 18V
RSENSE
0.05Ω
+
22µF
25V
CSS
0.01µF
RC
10k
CC
22OpF
VIN SENSE
RUN/SS PGATE
ITH LTC1771
VFB MODE
GND
M1
Si6447DQ
VIN
R2
1.64M
1%
L1
15µH
UPS5817
+
R1
1M
1%
CFF
5pF
Figure 1. High Efficiency Step-Down Converter
VOUT
3.3V
COUT 2A
150µF
6.3V
1771 F01
LTC1771 Efficiency
100
VIN = 5V
90 VIN = 10V
80 VIN = 15V
70
60
50
VOUT = 3.3V
40 RSENSE = 0.05Ω
0.1 1
10
100 1000
LOAD CURRENT (mA)
10000
1771 F01b
1
1 page  
LTC1771
PI FU CTIO S
RUN/SS (Pin 1): The voltage level on this pin controls
shutdown/run mode (ground = shutdown, open/high =
run). Connecting an external capacitor to this pin provides
soft-start.
ITH (Pin 2): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 3V.
VFB (Pin 3): Feedback of Output Voltage for Comparison
to Internal 1.23V Reference. An external resistive divider
across the output is returned to this pin.
GND (Pin 4): Ground Pin.
PGATE (Pin 5): High Current Gate Driver for External
P-Channel MOSFET Switch. Voltage swing is from ground
to VIN.
VIN (Pin 6): Main Input Voltage Supply Pin.
SENSE (Pin 7): Current Sense Input for Monitoring Switch
Current. Maximum switch current and Burst Mode
threshold is programmed with an external resistor be-
tween SENSE and VIN.
MODE (Pin 8): Burst Mode Enable/Disable Pin. Connect-
ing this pin to VIN (or above 2V) enables Burst Mode
operation, while connecting this pin to ground disables
Burst Mode operation. Do not leave floating.
W
FUNCTIONAL BLOCK DIAGRA
VIN
CSS RUN/SS
1
1µA
MODE
(BURST ENABLE)
8
READY
1.23V
VOUT
+ ON
SOFT-START
EA
–
10% CURRENT
*
ITH
2
RC
CC GND
4
2V
1V
–
B
1V +
SLEEP
READY
*OPTIONAL FOR FOLDBACK
CURRENT LIMITING
MODE
ON TRIGGER
1-SHOT
STRETCH
3.5µs
1.23V
REFERENCE
10% CURRENT
C
ON
VIN
6
22k
VIN
+
CIN
RSENSE
SENSE
7
250k
BLANKING
VIN
PGATE
5
D1
L
R2
VFB
3
R1
VOUT
+
COUT
1771 BD
5
5 Page 
LTC1771
APPLICATIO S I FOR ATIO
limiting should be added to reduce the current in propor-
tion to the severity of the fault.
Foldback current limiting is implemented by adding two
diodes in series between the output and the ITH pin as
shown in the Functional Diagram. In a hard short (VOUT =
0V) the current will be reduced to approximately 25% of
the maximum output current.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest amount of time
that the LTC1771 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the
P-channel MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
tON
=
tOFF
VOUT
VIN −
+ VD
VOUT
>
tON(MIN)
where tOFF = 3.5µs and tON(MIN) is generally about 0.4µs
for the LTC1771.
As the on-time approaches tON(MIN), the LTC1771 will
remain in Burst Mode operation for an increasingly larger
portion of the load range (see Figure 3) and at or below
tON(MIN) will remain in Burst Mode operation 100% of the
time. The output voltage will continue to be regulated, but
the ripple current and ripple voltage will increase.
100
80
60
Mode Pin
Burst Mode operation is disabled by pulling MODE (Pin 8)
below 0.5V. Disabling Burst Mode operation provides a
low noise output spectrum, useful for reducing both audio
and RF interference. It does this by keeping the frequency
constant (for fixed VIN) down to much lower load current
(1% to 2% of IMAX) and reducing the amount of output
voltage and current ripple at light loads. When Burst Mode
operation is disabled, efficiency is reduced at light loads
and no load supply current increases to 175µA.
Low Supply Operation
Although the LTC1771 can function down to 2.8V, the
maximum allowable output current is reduced when VIN
decreases below 3.2V. Figure 4 shows the amount of
change as the supply is reduced below 3.2V, where 100%
of maximum load equals 0.1/RSENSE. To ensure adequate
output current at VIN < 3.2V, simply lower RSENSE by the
same percentage as the current reduction in Figure 4.
140
120
100
80
60
40
20
0
2.5 3.0 3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
1771 F04
Figure 4. Maximum Load vs Input Voltage
40
20
0
0 0.5 1.0 1.5 2.0 2.5
ON-TIME (µs)
1771 F03
Figure 3. Burst Threshold vs On-Time
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1771. These items are also illustrated graphically in
the layout diagram of Figure 5. Check the following in your
layout:
1. Is the Schottky diode closely connected to the drain of
the external MOSFET and the input cap ground?
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC1771.PDF ] | |
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