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PDF LTC2402I Data sheet ( Hoja de datos )
| Número de pieza | LTC2402I | |
| Descripción | 1-/2-Channel 24-Bit uPower No Latency ADC in MSOP-10 | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2402I (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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Final Electrical Specifications
LTC2401/LTC2402
1-/2-Channel 24-Bit µPower
No Latency ∆ΣTMADC in MSOP-10
FEATURES
DESCRIPTIO
January 2000
s 24-Bit ADC in Tiny MSOP-10 Package
s 1- or 2-Channel Inputs
s Automatic Channel Selection (Ping-Pong) (LTC2402)
s Zero Scale and Full Scale Set for Reference
and Ground Sensing
s 4ppm INL, No Missing Codes
s 4ppm Full-Scale Error
s 0.5ppm Offset
s 0.6ppm Noise
s Internal Oscillator—No External Components Required
s 110dB Min, 50Hz/60Hz Notch Filter
s Single Conversion Settling Time for
Multiplexed Applications
s Reference Input Voltage: 0.1V to VCC
s Live Zero—Extended Input Range Accommodates
12.5% Overrange and Underrange
s Single Supply 2.7V to 5.5V Operation
s Low Supply Current (200µA) and Auto Shutdown
U
APPLICATIO S
s Weight Scales
s Direct Temperature Measurement
s Gas Analyzers
s Strain-Gage Transducers
s Instrumentation
s Data Acquisition
s Industrial Process Control
The LTC®2401/LTC2402 are 1- and 2-channel 2.7V to
5.5V micropower 24-bit analog-to-digital converters with
an integrated oscillator, 4ppm INL and 0.6ppm RMS
noise. These ultrasmall devices use delta-sigma technol-
ogy and a new digital filter architecture that settles in a
single cycle. This eliminates the latency found in conven-
tional ∆Σ converters and simplifies multiplexed applica-
tions.
Through a single pin, the LTC2401/LTC2402 can be
configured for better than 110dB rejection at 50Hz or
60Hz ±2%, or can be driven by an external oscillator for
a user defined rejection frequency in the range 1Hz to
120Hz. The internal oscillator requires no external fre-
quency setting components.
These converters accept an external reference voltage
from 0.1V to VCC. With an extended input conversion
range of –12.5% VREF to 112.5% VREF (VREF = FSSET –
ZSSET), the LTC2401/LTC2402 smoothly resolve the off-
set and overrange problems of preceding sensors or
signal conditioning circuits.
The LTC2401/LTC2402 communicate through a 2- or
3-wire digital interface that is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
TYPICAL APPLICATIO
2.7V TO 5.5V
1µF
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
ANALOG
INPUT RANGE
–0.12VREF TO 1.12VREF
(VREF = FSSET – ZSSET)
0V TO FSSET – 100mV
1
VCC
10
FO
LTC2402
2
FSSET
9
SCK
3
CH1
SDO 8
4
CH0
7
CS
56
ZSSET GND
VCC
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
3-WIRE
SPI INTERFACE
24012 TA01
Pseudo Differential Bridge Digitizer
1
VCC
2 LTC2402
FSSET SCK 9
4
CH0
8
SDO
3
CH1
CS 7
2.7V TO 5.5V
3-WIRE
SPI INTERFACE
5
ZSSET
GND
6
10
FO
INTERNAL OSCILLATOR
60Hz REJECTION
24012TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1
1 page  
LTC2401/LTC2402
PIN FUNCTIONS
VCC (Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 4) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
FSSET (Pin 2): Full-Scale Set Input. This pin defines the
full-scale input value. When VIN = FSSET, the ADC outputs
full scale (FFFFFH). The total reference voltage is
FSSET – ZSSET.
CH0, CH1 (Pins 4, 3): Analog Input Channels. The input
voltage range is – 0.125 • VREF to 1.125 • VREF. For
VREF > 2.5V, the input voltage range may be limited by the
absolute maximum rating of – 0.3V to VCC + 0.3V. Conver-
sions are performed alternately between CH0
and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on
the LTC2401.
ZSSET (Pin 5): Zero-Scale Set Input. This pin defines the
zero-scale input value. When VIN = ZSSET, the ADC
outputs zero scale (00000H).
GND (Pin 6): Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should
be connected directly to a ground plane through a mini-
mum length trace or it should be the single-point-ground
in a single-point grounding system.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
SDO (Pin 8): Three-State Digital Output. During the data
output period, this pin is used for serial data output. When
the chip select CS is HIGH (CS = VCC), the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status out-
put. The conversion status can be observed by pulling CS
LOW.
SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In the External Serial Clock Operation mode, SCK
is used as digital input for the external serial interface. An
internal pull-up current source is automatically activated
in Internal Serial Clock Operation mode. The Serial Clock
mode is determined by the level applied to SCK at power
up and the falling edge of CS.
FO (Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter’s
first null is located at 50Hz. When the FO pin is connected
to GND (FO = 0V), the converter uses its internal oscillator
and the digital filter’s first null is located at 60Hz. When FO
is driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its clock and the digital
filter first null is located at a frequency fEOSC/2560.
5
5 Page 
LTC2401/LTC2402
APPLICATIO S I FOR ATIO
for the forward and return paths (R1 = R2), the auxiliary
channel on the LTC2402 can measure this drop. These
errors are then removed with simple digital correction.
The result of the first conversion on CH0 corresponds to
an input voltage of VRTD + R1 • IEXCITATION. The result of the
second conversion (CH1) is – R1 • IEXCITATION. Note, the
LTC2402’s input range is not limited to the supply rails, it
has underrange capabilities. The device’s input range is
– 300mV to VREF + 300mV. Adding the two conversion
results together, the voltage drop across the RTD’s leads
are cancelled and the final result is VRTD.
An Isolated, 24-Bit Data Acquisition System
The LTC1535 is useful for signal isolation. Figure 9 shows
a fully isolated, 24-bit differential input A/D converter
implemented with the LTC1535 and LTC2402. Power on
the isolated side is regulated by an LT1761-5.0 low noise,
low dropout micropower regulator. Its output is suitable
for driving bridge circuits and for ratiometric applications.
During power-up, the LTC2402 becomes active at VCC =
2.3V, while the isolated side of the LTC1535 must wait for
VCC2 to reach its undervoltage lockout threshold of 4.2V.
Below 4.2V, the LTC1535’s driver outputs Y and Z are in a
high impedance state, allowing the 1kΩ pull-down to
define the logic state at SCK. When the LTC2402 first
becomes active, it samples SCK; a logic “0” provided by
the 1kΩ pull-down invokes the external serial clock mode.
In this mode, the LTC2402 is controlled by a single clock
line from the nonisolated side of the barrier, through the
LTC1535’s driver output Y. The entire power-up sequence,
from the time power is applied to VCC1 until the LT1761’s
output has reached 5V, is approximately 1ms.
Data returns to the nonisolated side through the LTC1535’s
receiver at RO. An internal divider on receiver input B sets
a logic threshold of approximately 3.4V at input A, facili-
tating communications with the LTC2402’s SDO output
without the need for any external components.
1/2 BAT54C
LT1761-5
+ 10µF
IN OUT
16V
TANT
SHDN BYP
GND
T1 1µF
10µF
+
10µF
10V
TANT
“SDO”
“SCK”
LOGIC 5V
1/2 BAT54C
RO ST1 ST2
RE
DE
LTC1535
DI VCC1 G1 G2
VCC2
A
B
Y
Z
2
+ 10µF
10V
TANT
2
1k
10µF +
1 10V
12
TANT
ISOLATION
1 BARRIER
= LOGIC COMMON
1
= FLOATING COMMON
2
2
T1 = COILTRONICS CTX02-14659
OR SIEMENS B78304-A1477-A3
10µF
CERAMIC
LTC2402
FO VCC
SCK FSSET
SDO CH1
CS CH0
GND ZSSET
2
2
24012 F09
Figure 9. Complete, Isolated 24-Bit Data Acquisition System
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LTC2402I.PDF ] | |
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