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부품번호 | 100301QC 기능 |
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기능 | Low Power Triple 5-Input OR/NOR Gate | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 7 페이지수
August 1989
Revised August 2000
100301
Low Power Triple 5-Input OR/NOR Gate
General Description
The 100301 is a monolithic triple 5-input OR/NOR gate. All
inputs have 50 kΩ pull-down resistors and all outputs are
buffered.
Features
s 23% power reduction of the 100101
s 2000V ESD protection
s Pin/function compatible with 100101
s Voltage compensated operating range = −4.2V to −5.7V
s Available to industrial grade temperature range
(PLCC package only)
Ordering Code:
Order Number Package Number
Package Description
100301SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100301PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100301QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100301QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
Dna, Dnb, Dnc
Oa, Ob, Oc
Oa, Ob, Oc
Description
Data Inputs
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS010579
28-Pin PLCC
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Commercial Version (Continued)
SOIC and PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = 0°C
Min Max
TC = +25°C
Min Max
TC = +85°C
Min Max
Units
Conditions
tPLH
tPHL
tTLH
tTHL
tOSHL
Propagation Delay
Data to Output
Transition Time
20% to 80%, 80% to 20%
Maximum Skew Common Edge
Output-to-Output Variation
0.50
1.00
0.50
1.05
0.50
1.10
0.40
1.10
0.40
1.10
0.40
1.10
240 240 240
Figures 1, 2
ns
(Note 5)
ns Figures 1, 2
PLCC Only
ps (Note 6)
Data to Output Path
tOSLH
Maximum Skew Common Edge
Output-to-Output Variation
PLCC Only
330 330 330 ps (Note 6)
Data to Output Path
tOST
Maximum Skew Opposite Edge
Output-to-Output Variation
PLCC Only
330 330 330 ps (Note 6)
Data to Output Path
tPS Maximum Skew
Pin (Signal) Transition Variation
PLCC Only
230 230 230 ps (Note 6)
Data to Output Path
Note 5: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching.
Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
Industrial Version
PLCC DC Electrical Characteristics (Note 7)
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C
Symbol
Parameter
TC = −40°C
Min Max
TC = 0°C to +85°C
Min Max
Units
Conditions
VOH Output HIGH Voltage
−1085 −870 −1025 −870
mV VIN = VIH(Max)
Loading with
VOL Output LOW Voltage
−1830 −1575 −1830 −1620
mV or VIL(Min)
50Ω to −2.0V
VOHC
Output HIGH Voltage
−1095
−1035
mV VIN = VIH(Min)
Loading with
VOLC
Output LOW Voltage
−1565
−1610
mV or VIL(Max)
50Ω to −2.0V
VIH Input HIGH Voltage
−1170 −870 −1165 −870
mV Guaranteed HIGH Signal for All Inputs
VIL Input LOW Voltage
−1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for All Inputs
IIL Input LOW Current
0.50 0.50
µA VIN = VIL(Min)
IIH Input HIGH Current
240 240 µA VIN = VIH(Max)
IEE Power Supply Current
−29 −15 −29 −15 mA Inputs Open
Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −40°C
Min Max
TC = +25°C
Min Max
TC = +85°C
Min Max
Units
tPLH Propagation Delay
tPHL Data to Output
0.40
1.00
0.50
1.05
0.50
1.10
ns
tTLH Transition Time
tTHL 20% to 80%, 80% to 20%
0.30
1.10
0.40
1.10
0.40
1.10
ns
Note 8: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching.
Conditions
Figures 1, 2
(Note 8)
Figures 1, 2
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4
4페이지 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7 www.fairchildsemi.com
7페이지 | |||
구 성 | 총 7 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
100301QC | Low Power Triple 5-Input OR/NOR Gate | Fairchild Semiconductor |
100301QI | Low Power Triple 5-Input OR/NOR Gate | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |