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PDF DALC208 Data sheet ( Hoja de datos )

Número de pieza DALC208
Descripción LOW CAPACITANCE DIODE ARRAY
Fabricantes STMicroelectronics 
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No Preview Available ! DALC208 Hoja de datos, Descripción, Manual

®
Application Specific Discretes
A.S.D.TM
DALC208SC6
LOW CAPACITANCE
DIODE ARRAY
MAIN APPLICATIONS
Where ESD and/or over and undershoot protection
for datalines is required :
Sensitive logic input protection
Microprocessor based equipment
Audio / Video inputs
Portable electronics
Networks
ISDN equipment
USB interface
DESCRIPTION
The DALC208SC6 diode array is designed to
protect components which are connected to data
and transmission lines from overvoltages caused
by electrostatic discharge (ESD) or other
transients. It is a rail-to-rail protection device also
suited for overshoot and undershoot suppression
on sensitive logic inputs.
The low capacitance of the DALC208SC6
prevents from significant signal distortion.
1
SOT23-6L (SC74)
FUNCTIONAL DIAGRAM
FEATURES
PROTECTION OF 4 LINES
PEAK REVERSE VOLTAGE:
VRRM = 9 V per diode
VERY LOW CAPACITANCE PER DIODE:
C < 5 pF
VERY LOW LEAKAGE CURRENT: IR < 1 µA
I/O 1
REF 2
I/O 2
I/O 4
REF 1
I/O 3
BENEFITS
Cost-effectiveness compared to discrete solution
High efficiency in ESD suppression
No significant signal distortion thanks to very low
capacitance
High reliability offered by monolithic integration
Lower PCB area consumption versus discrete
solution
COMPLIES WITH THE FOLLOWING STANDARDS :
IEC 1000-4-2
level 4
MIL STD 883C - Method 3015-6
(human body test)
class 3
February 1999 - Ed: 3A
1/10

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DALC208 pdf
HOW TO ENSURE A GOOD ESD PROTECTION
While the DALC208SC6 provides a high immunity
to ESD surge, an efficient protection depends on
the layout of the board. In the same way, with the
rail to rail topology, the track from the VREF2 pin to
the power supply +VCC and from the VREF1 pin to
GND must be as short as possible to avoid
overvoltages due to parasitic phenomena (see Fig.
A1).
It’s often harder to connect the power supply near
to the DALC208SC6 unlike the ground thanks to
the ground plane that allows a short connection.
DALC208SC6
Fig. A3: ESD behavior: measurements conditions
(with coupling capacitance).
TEST BOARD
ESD
SURGE
+5V
DALC
208
To ensure the same efficiency for positive surges
when the connections can’t be short enough, we
recommend to put close to the DALC208SC6,
between VREF2 and ground, a capacitance of
100nF to prevent from these kinds of overvoltage
disturbances (see Fig. A2).
The add of this capacitance will allow a better
protection by providing during surge a constant
voltage.
Fig. A3, A4a and A4b show the improvement of the
ESD protection according to the recommendations
described above.
Fig. A2: ESD behavior: optimized layout and add
of a capacitance of 100nF.
ESD
SURGE
Lw
C=100nF
REF2=+Vcc
Fig. A4a: Remaining voltage after the
DALC208SC6 during positive ESD surge.
IEC 1000-4-2
Air Discharge
(150pF/330 )
Vpp=15kV
I/O
VI/O
Vcl+ = Vcc+Vf surge >0
Vcl- = -Vf surge <0
REF1=GND
Fig. A4b: Remaining voltage after the
DALC208SC6 during negative ESD surge.
Vcl+
POSITIVE
SURGE
NEGATIVE
SURGE
t
t Vcl-
Important:
A main precaution to take is to put the protection
device closer to the disturbance source (generally
the connector).
Note: The measurements have been done with the DALC208SC6
in open circuit.
IEC 1000-4-2
Air Discharge
(150pF/330 )
Vpp=15kV
5/10

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