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부품번호 | DALC208SC6 기능 |
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기능 | LOW CAPACITANCE DIODE ARRAY | ||
제조업체 | STMicroelectronics | ||
로고 | |||
전체 10 페이지수
®
Application Specific Discretes
A.S.D.TM
DALC208SC6
LOW CAPACITANCE
DIODE ARRAY
MAIN APPLICATIONS
Where ESD and/or over and undershoot protection
for datalines is required :
Sensitive logic input protection
Microprocessor based equipment
Audio / Video inputs
Portable electronics
Networks
ISDN equipment
USB interface
DESCRIPTION
The DALC208SC6 diode array is designed to
protect components which are connected to data
and transmission lines from overvoltages caused
by electrostatic discharge (ESD) or other
transients. It is a rail-to-rail protection device also
suited for overshoot and undershoot suppression
on sensitive logic inputs.
The low capacitance of the DALC208SC6
prevents from significant signal distortion.
1
SOT23-6L (SC74)
FUNCTIONAL DIAGRAM
FEATURES
PROTECTION OF 4 LINES
PEAK REVERSE VOLTAGE:
VRRM = 9 V per diode
VERY LOW CAPACITANCE PER DIODE:
C < 5 pF
VERY LOW LEAKAGE CURRENT: IR < 1 µA
I/O 1
REF 2
I/O 2
I/O 4
REF 1
I/O 3
BENEFITS
Cost-effectiveness compared to discrete solution
High efficiency in ESD suppression
No significant signal distortion thanks to very low
capacitance
High reliability offered by monolithic integration
Lower PCB area consumption versus discrete
solution
COMPLIES WITH THE FOLLOWING STANDARDS :
IEC 1000-4-2
level 4
MIL STD 883C - Method 3015-6
(human body test)
class 3
February 1999 - Ed: 3A
1/10
DALC208SC6
TECHNICAL INFORMATION
SURGE PROTECTION
The DALC208SC6 is particularly optimized to
perform surge protection based on the rail to rail
topology.
The clamping voltage VCL can be calculated as
follow :
VCL+ = VREF2 + VF for positive surges
VCL- = VREF1 - VF for negative surges
with : VF = Vt + rd.Ip
(VF forward drop voltage) / (Vt forward drop
threshold voltage)
According to the curve Fig.5 on page 3, we
assume that the value of the dynamic resistance of
the clamping diode is typically rd = 0.7Ω and Vt =
1.2V.
For an IEC 1000-4-2 surge Level 4 (Contact
Discharge: Vg=8kV, Rg=330Ω), VREF2 = +5V,
VREF1 = 0V, and if in first approximation, we
assume that : Ip=Vg/Rg ≈ 24A.
So, we find:
VCL+ ≈ +23V
VCL- ≈ -18V
Note: the calculations do not take into account
phenomena due to parasitic inductances
APPLICATION EXAMPLE
If we consider that the connections from the pin
REF2 to VCC and from REF1 to GND are done by
two tracks of 10mm long and 0.5mm large; we
assume that the parasitic inductances of these
tracks are about 6nH.
So when an IEC 1000-4-2 surge occurs, due to the
rise time of this spike (tr=1ns), the voltage VCL has
an extra value equal to Lw.dI/dt.
The dI/dt is calculated as: di/dt = Ip/tr ≈ 24 A/ns
The overvoltage due to the parasitic inductances
is: Lw.di/dt = 6 x 24 ≈ 144V
By taking into account the effect of these parasitic
inductances due to unsuitable layout, the clamping
voltage will be :
VCL+ = +23 + 144 ≈ 167V
VCL- = -18 - 144 ≈ -162V
We can reduce as much as possible these
phenomena with simple layout optimization.
It’s the reason why some recommendations have
to be followed (see paragraph "How to ensure a
good ESD protection").
Fig. A1: ESD behavior; parasitic phenomena due to unsuitable layout.
4/10
ESD
SURGE
Lw
Lw di
Vf dt
I/O
REF2=+Vcc
VI/O
Lw di
dt
Vcl+ =
Vcc+Vf+
Lw
di
dt
Vcl- =
-Vf-
Lw
di
dt
surge >0
surge <0
REF1=GND
Vcl+
167V
Lw di
dt
POSITIVE
SURGE
Vcc+Vf
tr=1ns
t
tr=1ns
-Vf
-Lw di
dt
NEGATIVE
SURGE
-162V
Vcl-
t
4페이지 3- Analog Crosstalk
Fig. A7: Analog crosstalk measurements.
TRACKING GENERATOR
50Ω
+5V
Vg
Vin
TEST BOARD
DALC
208
C=100nF
DALC208SC6
SPECTRUM ANALYSER
Vout
50Ω
Figure A7 gives the measurement circuit for the
analog application. In usual frequency range of
analog signals (up to 100MHz) the effect on
disturbed line is less than -45 dBm (please see Fig.
A8).
Fig. A8: Analog crosstalk results.
dBm
0
-20
-40
-60
Fig. A9: Measurement conditions.
TRACKING GENERATOR
50Ω
+5V
Vg
Vin
TEST BOARD
DALC
208
C=100nF
SPECTRUM ANALYSER
Vout
50Ω
-80
-100
1
10 100
f(MHz)
1,000
As the DALC208SC6 is designed to protect high
speed data lines, it must ensure a good
transmission of operating signals. The attenuation
curve give such an information.
Fig. A10: DALC206SC6 attenuation.
dBm
0
-10
Fig. A10 shows that the DALC208SC6 is well
suitable for data line transmission up to 100 Mbit/s
while it works as a filter for undesirable signals as
GSM (900MHz).
-20
-30
1
10 100
f(MHz)
1,000
7/10
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부품번호 | 상세설명 및 기능 | 제조사 |
DALC208SC6 | LOW CAPACITANCE DIODE ARRAY | STMicroelectronics |
DALC208SC6Y | Automotive low capacitance diode array | STMicroelectronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |