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PDF CY7C371I Data sheet ( Hoja de datos )
| Número de pieza | CY7C371I | |
| Descripción | UltraLogic 32-Macrocell Flash CPLD | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
UltraLogic™ 32-Macrocell Flash CPLD
Features
• 32 macrocells in two logic blocks
• 32 I/O pins
• Five dedicated inputs including two clock pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— fMAX = 143 MHz
— tPD= 8.5 n3s
— tS = 5 ns
— tCO = 6 ns
• Fully PCI-compliant
• 3.3V or 5.0V I/O operation
• Available in 44-pin PLCC, and TQFP packages
• Pin-compatible with the CY7C372i
Functional Description
The CY7C371i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C371i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C371i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISREN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
The 32 macrocells in the CY7C371i are divided between two
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Like all members of the FLASH370i family, the CY7C371i is rich
in I/O resources. Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins on the CY7C371i.
In addition, there are three dedicated inputs and two
input/clock pins.
Logic Block Diagram
Clock
Inputs Inputs
16 I/Os
I/O0–I/O15
3
INPUT
MACROCELLS
2
LOGIC
BLOCK
A
36
16
PIM
2
INPUT/CLOCK
MACROCELLS
2
LOGIC
36 BLOCK
B
16
16 I/Os
I/O16–I/O31
16 16
Selection Guide
7C371i-143 7C371i-110 7C371i-83 7C371iL-83 7C371i-66 7C371iL-66
Maximum Propagation Delay[1], tPD
8.5
10
12
12
15
15
Minimum Set-up, tS
Maximum Clock to Output[1], tCO
5 68
6 6.5 8
8 10 10
8 10 10
Typical Supply Current, ICC Comm./Ind.
75
75 75
45
75
45
Note:
1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.
Unit
ns
ns
ns
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03032 Rev. *A
Revised April 19, 2004
1 page  
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
Inductance[8]
Parameter
L
Description
Test Conditions
Maximum Pin Inductance VIN = 5.0V at f= 1 MHz
44-Lead TQFP
2
Endurance Characteristics[8]
Parameter
Description
N Maximum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
44-Lead PLCC Unit
5 nH
Max.
100
Unit
Cycles
AC Test Loads and Waveforms
238Ω (COM'L)
319Ω (MIL)
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
(a)
170Ω (COM'L)
236Ω (MIL)
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
99Ω (COM'L)
136Ω (MIL)
2.08V(COM'L)
OUTPUT
2.13V(MIL)
238Ω (COM'L)
319Ω (MIL)
170Ω (COM'L)
236Ω (MIL)
(b)
3.0V
GND
< 2 ns
ALL INPUT PULSES
90%
10%
(c)
90%
10%
< 2 ns
Parameter[11]
tER(–)
Vx
1.5V
Output Waveform Measurement Level
VOH
0.5V
VX
tER(+)
2.6V
0.5V
VOL
VX
tEA(+)
1.5V
0.5V
VX
VOH
tEA(–)
Vthe
VX
0.5V
VOL
Note:
11. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
Document #: 38-03032 Rev. *A
Page 5 of 12
5 Page 
USE ULTRA37000™ FOR
ALL NEW DESIGNS
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
CY7C371i
51-85003-*A
FLASH370, FLASH370i, ISR, UltraLogic, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor
Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-03032 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY7C371I.PDF ] | |
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