PDF CY7C43642AV-15AC Data sheet ( Hoja de datos )

Número de pieza	CY7C43642AV-15AC
Descripción	3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY7C43642AV CY7C43662AV CY7C43682AV 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO Features • 3.3V high-speed, low-power, bidirectional, First-In First-Out (FIFO) memories • 1K ×36 ×2 (CY7C43642AV) • 4K x36 x2 (CY7C43662AV) • 16K x36 x2 (CY7C43682AV) • 0.25-micron CMOS for optimum speed/power • High-speed 133-MHz operation (7.5-ns Read/Write cycle times) Logic Block Diagram • Low power — ICC = 60 mA — ISB = 10 mA • Fully asynchronous and simultaneous Read and Write operations permitted • Mailbox bypass register for each FIFO • Parallel Programmable Almost Full and Almost Empty flags • Retransmit function • Standard or FWFT user-selectable mode • 120-pin TQFP package • Easily expandable in width and depth CLKA CSA W/RA ENA MBA RT2 MRST1 FFA/IRA AFA FS0 FS1 A0–35 EFA/ORA AEA Port A Control Logic FIFO1, Mail1 Reset Logic MBF2 Mail1 Register 1K/4K/16K × 36 Dual Ported Memory (FIFO1) Write Pointer Read Pointer Status Flag Logic Programmable Flag Offset Registers Timing Mode Status Flag Logic Write Pointer Read Pointer 1K/4K/16K × 36 Dual Ported Memory (FIFo2) Mail2 Register Port B Control Logic MBF1 CLKB CSB W/RB ENB MBB RT1 EFB/ORB AEB B0–35 FWFT/STAN FFB/IRB AFB FIFO2, Mail2 Reset Logic MRST2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-06020 Rev. C Revised December 26, 2002 1 page CY7C43642AV CY7C43662AV CY7C43682AV Pin Definitions (continued) Signal Name Description MRST2 FIFO2 Master Reset RT1 RT2 W/RA W/RB Retransmit FIFO1 Retransmit FIFO2 Port A Write/Read Select Port B Write/Read Select I/O Function I A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location of memory and sets the Port A output register to all zeroes. A LOW pulse on MRST2 selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRST2 is LOW. I A LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by bringing the Read pointer back to location zero. The user will still need to perform Read opera- tions to retransmit the data. Retransmit function applies to CY standard mode only. I A LOW strobe on this pin will retransmit the data on FIFO2. This is achieved by bringing the Read pointer back to location zero. The user will still need to perform Read opera- tions to retransmit the data. Retransmit function applies to CY standard mode only. I A HIGH selects a Write operation and a LOW selects a Read operation on Port A for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance state when W/RA is HIGH. I A LOW selects a Write operation and a HIGH selects a Read operation on Port B for a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance state when W/RB is LOW. Document #: 38-06020 Rev. C Page 5 of 30 5 Page CY7C43642AV CY7C43662AV CY7C43682AV AC Test Loads and Waveforms (–10 and –15) 3.3V R1 = 330Ω OUTPUT [17] CL = 30 pF R2 = 680Ω INCLUDING JIG AND SCOPE AC Test Loads and Waveforms (–7) VCC/2 50 Ω I/O Z0 = 50Ω 3.0V GND ≤ 3 ns ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns 3.0V GND ≤ 3 ns ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns Switching Characteristics Over the Operating Range Parameter Description fS tCLK tCLKH tCLKL tDS Clock Frequency, CLKA or CLKB Clock Cycle Time, CLKA or CLKB Pulse Duration, CLKA or CLKB HIGH Pulse Duration, CLKA or CLKB LOW Set-Up Time, A0–35 before CLKA↑ and B0–35 before CLKB↑ tENS Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB, W/RB, ENB, and MBB before CLKB↑ tRSTS Set-Up Time, MRST1, MRST2, RT1 or RT2 LOW before CLKA↑ or CLKB↑[17] tFSS Set-Up Time, FS0 and FS1 before MRST1 and MRST2 HIGH tFWS tDH tENH Set-Up Time, FWFT before CLKA↑ Hold Time, A0–35 after CLKA↑ and B0–35 after CLKB↑ Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB after CLKB↑ tRSTH Hold Time, MRST1, MRST2, RT1 or RT2 LOW after CLKA↑ or CLKB↑[17] Notes: 17. CL = 5 pF for tDIS. 18. Requirement to count the clock edge as one of at least four needed to reset a FIFO. CY7C43642/ 62/82AV –7 Min. Max. 133 7.5 3.5 3.5 3 3 2.5 5 0 0 0 1 CY7C43642/ 62/82AV –10 Min. Max. 100 10 4 4 4 4 4 7 0 0 0 2 CY7C43642/ 62/82AV –15 Min. Max. 67 15 6 6 5 5 5 7.5 0 0 0 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns Document #: 38-06020 Rev. *C Page 11 of 30 11 Page

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