PDF CY7C43682-15AI Data sheet ( Hoja de datos )

Número de pieza	CY7C43682-15AI
Descripción	1K/4K/16K x36 x2 Bidirectional Synchronous FIFO
Fabricantes	Cypress Semiconductor
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CY7C43642 CY7C43662 CY7C43682 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO Features • High-speed, low-power, bidirectional, First-In, First-Out (FIFO) memories • 1Kx36x2 (CY7C43642) • 4Kx36x2 (CY7C43662) • 16Kx36x2 (CY7C43682) • 0.35-micron CMOS for optimum speed/power • High speed 133-MHz operation (7.5-ns read/write cycle times) Logic Block Diagram • Low power — ICC= 100 mA — ISB= 10 mA • Fully asynchronous and simultaneous read and write operation permitted • Mailbox bypass register for each FIFO • Parallel Programmable Almost Full and Almost Empty flags • Retransmit function • Standard or FWFT mode user selectable • 120-pin TQFP packaging • Easily expandable in width and depth CLKA CSA W/RA ENA MBA RT2 RST1 FFA/IRA AFA FS0 FS1 A0–35 EFA/ORA AEA Port A Control Logic FIFO1, Mail1 Reset Logic MBF2 Mail1 Register 1K/4K/16K x36 Dual Ported Memory Write Pointer Read Pointer Status Flag Logic Programmable Flag Offset Registers Timing Mode Status Flag Logic Write Pointer Read Pointer 256/512/1K 4K/16K x36 Dual Ported Memory Mail2 Register Port B Control Logic MBF1 CLKB CSB W/RB ENB MBB RT1 EFB/ORB AEB B0–35 FWFT/STAN FFB/IRB AFB FIFO2, Mail2 Reset Logic RST2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-06019 Rev. B Revised December 26, 2002 1 page CY7C43642 CY7C43662 CY7C43682 Pin Definitions (continued) Signal Name Description FS1 Flag Offset Select 1 FS0 Flag Offset Select 0 MBA Port A Mailbox Select MBB Port B Mailbox Select MBF1 MBF2 RT1 RT2 W/RA W/RB RST1 Mail1 Register Flag Mail2 Register Flag Retransmit FIFO1 Retransmit FIFO2 Port A Write/ Read Select Port B Write/ Read Select FIFO1 Master Reset RST2 FIFO2 Master Reset I/O Function I The LOW-to-HIGH transition of a FIFO’s reset input latches the values of FS0 and FS1. If either FS0 or FS1 is HIGH when a reset input goes HIGH, one of the three preset I values (8, 16, or 64) is selected as the offset for the FIFO’s Almost Full and Almost Empty flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 Almost Empty offsets for both FIFOs. I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When a read operation is performed on Port A, a HIGH level on MBA selects data from the Mail2 register for output and a LOW level selects FIFO2 output register data for output. When a write operation is performed on Port A, a HIGH level on MBA will write the data into Mail1 register while a LOW level will write the data into FIFO1. I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When a read operation is performed on Port B, a HIGH level on MBB selects data from the Mail1 register for output and a LOW level selects FIFO1 output register data for output. When a write operation is performed on Port B, a HIGH level on MBB will write the data into Mail2 register while a LOW level will write the data into FIFO2. O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1 register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1. O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2 register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2. I A LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by bringing the read pointer back to location zero. The user will still need to perform read operations to retransmit the data. Retransmit function applies to CY standard mode only. I A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing the read pointer back to location zero. The user will still need to perform read operations to retransmit the data. Retransmit function applies to CY standard mode only. I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the HIGH impedance state when W/RA is HIGH. I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the HIGH impedance state when W/RB is LOW. I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B output register to all zeroes. A LOW pulse on RST1 selects the programming method (serial or parallel) and one of three programmable flag default offsets. It also configures Port A for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST1 is LOW. I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port B output register to all zeroes. A LOW pulse on RST2 selects the programming method (serial or parallel) and one of three programmable flag default offsets. It also configures Port B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST2 is LOW. Signal Description Reset (RST1, RST2) Each of the two FIFO memories of the CY7C436X2 undergoes a complete reset by taking its associated Master Reset (RST1, RST2) input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset inputs can switch asynchronously to the clocks. A Master Reset initializes the internal read and write pointers and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag (AFA, AFB) HIGH. A Master Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. A Master Document #: 38-06019 Rev. B Page 5 of 30 5 Page AC Test Loads and Waveforms (-10 and -15) 5V OUTPUT R1 = 1.1kΩ CL = 30 pF R2 = 680Ω INCLUDING JIG AND SCOPE AC Test Loads and Waveforms (-7) VCC/2 50 Ω I/O Z0 = 50Ω CY7C43642 CY7C43662 CY7C43682 3.0V GND ≤ 3 ns ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns 3.0V GND ≤ 3 ns ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns Switching Characteristics Over the Operating Range CY7C43642/62/82 CY7C43642/62/82 CY7C43642/62/82 -7 -10 -15 Parameter Description Min. Max. Min. Max. Min. Max. Unit fS Clock Frequency, CLKA or CLKB 133 100 tCLK Clock Cycle Time, CLKA or CLKB 7.5 10 15 tCLKH Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 tCLKL Pulse Duration, CLKA or CLKB LOW 3.5 4 6 tDS Set-up Time, A0–35 before CLKA↑ and B0–35 3 before CLKB↑ 4 5 67 MHz ns ns ns ns tENS Set-up Time, CSA, W/RA, ENA, and MBA before 3 CLKA↑; CSB, W/RB, ENB, and MBB before CLKB↑ 4 5 ns tRSTS Set-up Time, RST1, RST2, RT1 or RT2 LOW before CLKA↑ or CLKB↑[17] 2.5 4 5 ns tFSS Set-up Time, FS0 and FS1 before RST1 and 6 RST2 HIGH 7 7.5 ns tSDS tSENS tFWS tDH Set-up Time, FS0 before CLKA↑ Set-up Time, FS1 before CLKA↑ Set-up Time, FWFT before CLKA↑ Hold Time, A0–35 after CLKA↑ and B0–35 after CLKB↑ 3 3 0 0 4 4 0 0 5 ns 5 ns 0 ns 0 ns tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB after CLKB↑ 0 0 0 ns tRSTH Hold Time, RST1, RST2, RT1 or RT2 LOW after CLKA↑ or CLKB↑[17] 1 2 4 ns tFSH Hold Time, FS0 and FS1 after RST1 and RST2 1 HIGH 1 2 ns tSDH Hold Time, FS0 after CLKA↑ 0 0 0 ns tSENH Hold Time, FS1 after CLKA↑ 0 0 0 ns Note: 17. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB cycle. Document #: 38-06019 Rev. *B Page 11 of 30 11 Page

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