CYWUSB6934-48LFXC Datasheet PDF - Cypress Semiconductor
| Part Number | CYWUSB6934-48LFXC | |
| Description | WirelessUSB LS 2.4-GHz DSSS Radio SoC | |
| Manufacturers | Cypress Semiconductor | |
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CYWUSB6932
CYWUSB6934
WirelessUSB™ LS 2.4-GHz DSSS Radio SoC
1.0 Features
• 2.4-GHz radio transceiver
• Operates in the unlicensed Industrial, Scientific, and
Medical (ISM) band (2.4 GHz–2.483 GHz)
• -90-dBm receive sensitivity
• Up to 0 dBm output power
• Range of up to 10 meters or more
• Data throughput of up to 62.5 kbits/sec
• Highly integrated low cost, minimal number of external
components required
• Dual DSSS reconfigurable baseband correlators
• SPI microcontroller interface (up to 2-MHz data rate)
• 13-MHz ± 50-ppm input clock operation
• Low standby current < 1 µA
• Integrated 30-bit Manufacturing ID
• Operating voltage from 2.7V to 3.6V
• Operating temperature from 0° to 70°C
• Offered in a small footprint 48 Quad Flat Pack No Leads
(QFN)
2.0 Functional Description
The CYWUSB6932/CYWUSB6934 Integrated Circuits (ICs)
are highly integrated 2.4-GHz Direct Sequence Spread
Spectrum (DSSS) Radio System-on-Chip (SoC) ICs. From the
Serial Peripheral Interface (SPI) to the antenna, these ICs are
single-chip 2.4-GHz DSSS Gaussian Frequency Shift Keying
(GFSK) baseband modems that connect directly to a micro-
controller via simple serial interface.
The CYWUSB6932 transmit-only IC and the CYWUSB6934
transceiver IC are available in a small footprint 48-pin QFN
package.
3.0 Applications
• PC Human Interface Devices (HIDs)
• Mice
• Keyboards
• Joysticks
• Peripheral Gaming Devices
• Game Controllers
• Console Keyboards
• General
• Presenter Tools
• Remote Controls
• Consumer Electronics
• Barcode Scanners
• POS Peripherals
• Toys
DIOVAL
DIO
IRQ
SS
SCK
MISO
MOSI
RESET
PD
SERDES
A
DSSS
Baseband
A
Digital
SERDES
B
DSSS
Baseband
B
Synthesizer
GFSK
Modulator
GFSK
Demodulator
RFOUT
RFIN
CY WUSB6934Only
Figure 3-1. CYWUSB6932/CYWUSB6934 Simplified Block Diagram
Cypress Semiconductor Corporation •
Document 38-16007 Rev. *G
3901 North First Street
• San Jose, CA 95134 • 408-943-2600
Revised November 15, 2004
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CYWUSB6932
CYWUSB6934
5.2 DIO Interface
The DIO communications interface is an optional SERDES
bypass data-only transfer interface. In receive mode, DIO and
DIOVAL are valid after the falling edge of IRQ, which clocks
the data as shown in Figure 5-6. In transmit mode, DIO and
DIOVAL are sampled on the falling edge of the IRQ, which
clocks the data as shown in Figure 5-7. The application MCU
samples the DIO and DIOVAL on the rising edge of IRQ.
IRQ
DIOVAL
DIO
v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v...
data to mcu
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d...
Figure 5-6. DIO Receive Sequence
IRQ
DIOVAL
DIO
v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v...
data from mcu
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d...
Figure 5-7. DIO Transmit Sequence
5.3 Interrupts
The CYWUSB6932/CYWUSB6934 ICs feature three sets of
interrupts: transmit, receive (CYWUSB6934 only), and a wake
interrupt. These interrupts all share a single pin (IRQ), but can
be independently enabled/disabled. In transmit mode, all
receive interrupts are automatically disabled, and in receive
mode all transmit interrupts are automatically disabled.
However, the contents of the enable registers are preserved
when switching between transmit and receive modes.
Interrupts are enabled and the status read through 6 registers:
Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status
(Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit
Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake
Status (Reg 0x1D).
If more than 1 interrupt is enabled at any time, it is necessary
to read the relevant interrupt status register to determine which
event caused the IRQ pin to assert. Even when a given
interrupt source is disabled, the status of the condition that
would otherwise cause an interrupt can be determined by
reading the appropriate interrupt status register. It is therefore
possible to use the devices without making use of the IRQ pin
at all. Firmware can poll the interrupt status register(s) to wait
for an event, rather than using the IRQ pin.
The polarity of all interrupts can be set by writing to the Config-
uration register (Reg 0x05), and it is possible to configure the
IRQ pin to be open drain (if active low) or open source (if active
high).
5.3.1 Wake Interrupt
When the PD pin is low, the oscillator is stopped. After PD is
deasserted, the oscillator takes time to start, and until it has
done so, it is not safe to use the SPI interface. The wake
interrupt indicates that the oscillator has started, and that the
device is ready to receive SPI transfers.
The wake interrupt is enabled by setting bit 0 of the Wake
Enable register (Reg 0x1C, bit 0=1). Whether or not a wake
interrupt is pending is indicated by the state of bit 0 of the Wake
Status register (Reg 0x1D, bit 0). Reading the Wake Status
register (Reg 0x1D) clears the interrupt.
5.3.2 Transmit Interrupts
Four interrupts are provided to flag the occurrence of transmit
events. The interrupts are enabled by writing to the Transmit
Interrupt Enable register (Reg 0x0D), and their status may be
determined by reading the Transmit Interrupt Status register
(Reg 0x0E). If more than 1 interrupt is enabled, it is necessary
to read the Transmit Interrupt Status register (Reg 0x0E) to
determine which event caused the IRQ pin to assert.
The function and operation of these interrupts are described in
detail in Section 7.0.
5.3.3 Receive Interrupts
Eight interrupts are provided to flag the occurrence of receive
events, four each for SERDES A and B. In 64 chips/bit and 32
chips/bit DDR modes, only the SERDES A interrupts are
available, and the SERDES B interrupts will never trigger,
even if enabled. The interrupts are enabled by writing to the
Receive Interrupt Enable register (Reg 0x07), and their status
may be determined by reading the Receive Interrupt Status
register (Reg 0x08). If more than one interrupt is enabled, it is
necessary to read the Receive Interrupt Status register (Reg
0x08) to determine which event caused the IRQ pin to assert.
The function and operation of these interrupts are described in
detail in Section 7.0.
Document 38-16007 Rev. *G
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