|
|
PDF CY7C056V-15BAC Data sheet ( Hoja de datos )
| Número de pieza | CY7C056V-15BAC | |
| Descripción | 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C056V-15BAC (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
1
PRELIMINARY
CY7C056V
CY7C057V
3.3V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 16K x 36 organization (CY7C056V)
• 32K x 36 organization (CY7C057V)
• 0.25-micron CMOS for optimum speed/power
• High-speed access: 10/12/15/20 ns
• Low operating power
— Active: ICC = 260 mA (typical)
— Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
Logic Block Diagram
• Expandable data bus to 72 bits or more using Mas-
ter/Slave Chip Select when using more than one device
• On-Chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Byte Select on Left Port
• Bus Matching on Right Port
• Depth Expansion via dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Compact package
— 144-Pin TQFP (20 x 20 x 1.4 mm)
— 172-Ball BGA (1.0 mm pitch) (15 x 15 x .51 mm)
R/WL
B0–B3
CE0L
CE1L
OEL
I/O0L–I/O8L
I/O9L–I/O17L
I/O18L–I/O26L
I/O27L–I/O35L
Left
Port
CEL
Control
Logic
9
9
9
9
I/O
Control
I/O
Control
Right
Port
Control
Logic
CER
9
9
Bus
9 Match
9
R/WR
CE0R
CE1R
OER
BA
WA
9/18/36
I/OR
BM
SIZE
[1]
A0L–A13/14L
14/15
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
14/15
[1]
A0R–A13/14R
14/15
14/15
SEML
BUSYL[2]
INTL
Interrupt
Semaphore
Arbitration
SEMR
[2]
BUSYR
INTR
Notes:
1. A0–A13 for 16K; A0–A14 for 32K devices.
2. BUSY is an output in Master mode and an input in Slave mode.
M/S
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
April 27, 2000
1 page  
PRELIMINARY
CY7C056V
CY7C057V
Selection Guide
Maximum Access Time (ns)
Typical Operating Current (mA)
Typical Standby Current for ISB1 (mA) (Both Ports TTL Level)
Typical Standby Current for ISB3 (µA) (Both Ports CMOS
Level)
CY7C056V
CY7C057V
-10
10
260
60
10 µA
CY7C056V
CY7C057V
-12
12
250
55
10 µA
CY7C056V
CY7C057V
-15
15
240
50
10 µA
CY7C056V
CY7C057V
-20
20
230
45
10 µA
Pin Definitions
Left Port
A0L–A13/14L
SEML
CE0L, CE1L
INTL
BUSYL
I/O0L–I/O35L
OEL
R/WL
B0–B3
M/S
VSS
VDD
Right Port
A0R–A13/14R
SEMR
CE0R, CE1R
INTR
BUSYR
I/O0R–I/O35R
OER
R/WR
BM, SIZE
WA, BA
Description
Address (A0–A13 for 16K; A0–A14 for 32K devices)
Semaphore Enable
Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH)
Interrupt Flag
Busy Flag
Data Bus Input/Output
Output Enable
Read/Write Enable
Byte Select Inputs. Asserting these signals enables read and write oper-
ations to the corresponding bytes of the memory array.
See Bus Matching for details.
See Bus Matching for details.
Master or Slave Select
Ground
Power
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied .............................................–55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to VDD+0.5V
DC Input Voltage...................................–0.5V to VDD+0.5V[6]
Note:
6. Pulse width < 20 ns.
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Shaded areas contain advance information.
VDD
3.3V ± 165 mV
3.3V ± 165 mV
5
5 Page 
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[27, 28, 29, 30]
tWC
ADDRESS
OE
CE0, CE1[31, 32]
R/W
DATA OUT
DATA IN
tAW
CHIP SELECT VALID
tSA tPWE[30]
NOTE 34
tHZWE[33]
tSD
CY7C056V
CY7C057V
tHZOE[33]
tHA
tLZWE
tHD
NOTE 34
Write Cycle No. 2: CE Controlled Timing[27, 28, 29, 35]
ADDRESS
tWC
CE0, CE1[31, 32]
R/W
tSA
tAW
CHIP SELECT VALID
tSCE
DATA IN
tSD
tHA
tHD
Notes:
27. R/W must be HIGH during all address transitions.
28. A write occurs during the overlap (tSCE or tPWE) of CE0=VIL and CE1=VIH or SEM=VIL and B0–3 LOW.
29. tHA is measured from the earlier of CE0/CE1 or R/W or (SEM or R/W) going HIGH at the end of Write Cycle.
30. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.
31. To access RAM, CE0 = VIL, CE1=SEM = VIH.
32. To access byte B0, CE0 = VIL, B0 = VIL, CE1=SEM = VIH.
To access byte B1, CE0 = VIL, B1 = VIL, CE1=SEM = VIH.
To access byte B2, CE0 = VIL, B2 = VIL, CE1=SEM = VIH.
To access byte B3, CE0 = VIL, B3 = VIL, CE1=SEM = VIH.
33. Transition is measured ±150 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CE0 LOW and CE1 HIGH or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CY7C056V-15BAC.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C056V-15BAC | 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM | Cypress Semiconductor |
| CY7C056V-15BAI | 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |