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100323F 데이터시트 PDF




National Semiconductor에서 제조한 전자 부품 100323F은 전자 산업 및 응용 분야에서
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부품번호 100323F 기능
기능 Low Power Hex Bus Driver
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100323F 데이터시트, 핀배열, 회로
August 1998
100323
Low Power Hex Bus Driver
General Description
The 100323 is a monolithic device containing six bus drivers
capable of driving terminated lines with terminations as low
as 25. To reduce crosstalk, each output has its own re-
spective ground connection. Transition times were designed
to be longer than on other F100K devices. The driver itself
performs the positive logic AND of a data input (D1–D6) and
the OR of two select inputs (E and either DE1, DE2, or DE3).
Enabling of data is possible in multiples of two, i.e., 2, 4 or all
6 paths. All inputs have 50 kpull-down resistors.
The output voltage LOW level is designed to be more nega-
tive than normal ECL outputs (cut off state). This allows an
emitter-follower output transistor to turn off when the termi-
nation supply is −2.0V and thus present a high impedance to
the data bus.
Features
n 50% power reduction of the 100123
n 2000V ESD protection
n −4.2V to −5.7V operating range
n Drives 25load
Logic Symbol
Pin Names
D1– D6
DE1–DE3
E
O1– O6
Description
Data Inputs
Dual Enable Inputs
Common Enable Input
Data Outputs
DS100312-7
© 1998 National Semiconductor Corporation DS100312
www.national.com




100323F pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −55˚C
Min Max
TC = +25˚C
Min Max
TC = +125˚C
Min Max
Units
Conditions
tPZH
Propagation Delay
0.70 3.70 1.10 3.60 1.20 3.60 ns
Figures 1, 2
tPHZ
Data to Output
0.50 3.60 1.10 3.10 1.20 3.50
tPZH
Propagation Delay
0.60 3.60 1.10 3.60 1.30 3.80 ns
tPHZ Data Enable to Output
1.00 4.20 1.50 3.60 1.60 4.00
tPZH
Propagation Delay
0.70 3.60 1.00 3.50 1.20 3.60 ns
tPHZ Common Enable to Output 0.90 4.00 1.40 3.40 1.40 3.80
tTZH Transition Time
0.20 2.00 0.20 2.00 0.20 2.00 ns
tTHZ 20% to 80%, 80% to 20%
0.20 1.80 0.20 1.60 0.20 1.60
Note 7: The specified limits represent the “worst case” value for the parameter. Since these “worst case” values normally occur at the temperature extremes, ad-
ditional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
Note 8: Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
Test Circuitry
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1 and L2 = equal length 50impedance lines
RT = 50terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 25to GND
CL = Fixture and stray capacitance 3 pF
Pin numbers shown are for flatpak; for DIP see logic symbol
FIGURE 1. AC Test Circuit
DS100312-5
www.national.com
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100323F 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted
24 Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)
NS Package Number J24E
24 Lead Quad Cerpak (F)
NS Package Number W24B
7
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