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PDF CY7C341B Data sheet ( Hoja de datos )

Número de pieza CY7C341B
Descripción 192-Macrocell MAX EPLD
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! CY7C341B Hoja de datos, Descripción, Manual

USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C341B
192-Macrocell MAX® EPLD
Features
• 192 macrocells in 12 logic array blocks (LABs)
• Eight dedicated inputs, 64 bidirectional I/O pins
• Advanced 0.65-micron CMOS technology to increase
performance
• Programmable interconnect array
• 384 expander product terms
• Available in 84-pin HLCC, PLCC, and PGA packages
Functional Description
The CY7C341B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
100% user-configurable, allowing the devices to accom-
modate a variety of independent logic functions.
The 192 macrocells in the CY7C341B are divided into 12 Logic
Array Blocks (LABs), 16 per LAB. There are 384 expander
product terms, 32 per LAB, to be used and shared by the
Selection Guide
Maximum Access Time
7C341B-25
25
macrocells within each LAB. Each LAB is interconnected with
a programmable interconnect array, allowing all signals to be
routed throughout the chip.
The speed and density of the CY7C341B allows it to be used
in a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 37 times the functionality
of 20-pin PLDs, the CY7C341B allows the replacement of over
75 TTL devices. By replacing large amounts of logic, the
CY7C341B reduces board space, part count, and increases
system reliability.
Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8
macrocells are connected to I/O pins and eight are buried,
while for LABs B, C, D, E, H, I, J, and K, four macrocells are
connected to I/O pins and 12 are buried. Moreover, in addition
to the I/O and buried macrocells, there are 32 single product
term logic expanders in each LAB. Their use greatly enhances
the capability of the macrocells without increasing the number
of product terms in each macrocell.
7C341B-35
35
Unit
ns
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03016 Rev. *C
Revised April 22, 2004

1 page




CY7C341B pdf
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C341B
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................-65°C to +135°C
Ambient Temperature with
Power Applied............................................. –65°C to +135°C
Maximum Junction Temperature
(Under Bias)................................................................. 150°C
Supply Voltage to Ground Potential[1].............. −2.0V to +7.0V
DC Output Current, per Pin[1]..................... −25 mA to +25 mA
DC Input Voltage[1]................................................−2.0V to +7.0V
Operating Range[3]
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ± 5%
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
VCC
VOH
VOL
VIH
VIL
IIX
IOZ
tR (Recommended)
tF (Recommended)
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Current
Output Leakage Current
Input Rise Time
Input Fall Time
Test Conditions
Maximum VCC rise time is 10 ms
VCC = Min., IOH = –4.0 mA[2]
VCC = Min., IOL = 8 mA[2]
GND VIN VCC
VO = VCC or GND
Min.
4.75(4.5)
2.4
2.0
0.3
10
40
Capacitance
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 0V, f = 1.0 MHz
VOUT = 0V, f = 1.0 MHz
Max.
10
20
AC Test Loads and Waveforms
Max.
5.25(5.5)
0.45
VCC+ 0.3
0.8
+10
+40
100
100
Unit
V
V
V
V
V
µA
µA
ns
ns
Unit
pF
pF
5V
OUTPUT
R1 464
5V
OUTPUT
R1 464
50 pF
R2
250
5 pF
R2
250
INCLUDING
JIG AND
SCOPE (a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT (commercial/military)
OUTPUT
163
1.75V
3.0V
GND
< 6 ns
ALL INPUT PULSES
90%
10%
tR
90%
10%
< 6 ns
tF
Notes:
1. Minimum DC input is –0.3V. During transactions, input may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter
than 20 ns.
2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
3. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
Document #: 38-03016 Rev. *C
Page 5 of 12

5 Page





CY7C341B arduino
USE ULTRA37000™ FOR
ALL NEW DESIGNS
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
CY7C341B
84-Lead Windowed Pin Grid Array R84
51-85006-*A
51-80026-*B
MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All product and company
names mentioned in this document are trademarks of their respective holders.
Document #: 38-03016 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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