PDF CY7C343-30HMB Data sheet ( Hoja de datos )

Número de pieza	CY7C343-30HMB
Descripción	64-Macrocell MAX EPLD
Fabricantes	Cypress Semiconductor
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No Preview Available ! USE ULTRA37000™ FOR ALL NEW DESIGNS CY7C343 64-Macrocell MAX® EPLD Features • 64 MAX® macrocells in four LABs • Eightdedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology • Available in 44-pin HLCC, PLCC • Lowest power MAX device Functional Description The CY7C343 is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages. The CY7C343 contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks (LABs) connected through the Program- mable Inter-connect Array (PIA). There are eight input pins, one that doubles as a clock pin when needed. The CY7C343 also has 28 I/O pins, each connected to a macrocell (six for LABs A and C, and eight for LABs B and D). The remaining 36 macrocells are used for embedded logic. The CY7C343 is excellent for a wide range of both synchronous and asynchronous applications. Logic Block Diagram 9 INPUT 11 INPUT 12 INPUT 13 INPUT I/O PINS 2 4 5 6 7 8 LAB A MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 DEDICATED INPUTS SYSTEM CLOCK I/O PINS 15 16 17 18 19 20 22 23 MACROCELLS 7–16 LAB B MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21 MACROCELL 22 MACROCELL 23 MACROCELL 24 MACROCELLS 25–32 P I A (3, 14, 25, 36) (10, 21, 32, 43) VCC GND INPUT 35 INPUT/CLK 34 INPUT 33 INPUT 31 LAB D MACROCELL 56 MACROCELL 55 MACROCELL 54 MACROCELL 53 MACROCELL 52 MACROCELL 51 MACROCELL 50 MACROCELL 49 MACROCELLS 57–64 LAB C MACROCELL 38 MACROCELL 37 MACROCELL 36 MACROCELL 35 MACROCELL 34 MACROCELL 33 MACROCELLS 39–48 1 44 42 41 I/O PINS 40 39 38 37 30 29 28 I/O PINS 27 26 24 Selection Guide Maximum Access Time Maximum Operating Current Maximum Standby Current Commercial Military Industrial Commercial Military Industrial 7C343-20 20 135 225 225 125 200 200 7C343-25 25 135 225 225 125 200 200 7C343-30 30 135 225 225 125 200 200 7C343-35 35 135 225 225 125 200 200 Unit ns mA mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-03015 Rev. B Revised April 22, 2004 1 page USE ULTRA37000™ FOR ALL NEW DESIGNS CY7C343 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................ –65°C to +150°C Ambient Temperature with Power Applied.................................................. 0°C to +70°C Maximum Junction Temperature (Under Bias)................................................................. 150°C Supply Voltage to Ground Potential ............... –2.0V to +7.0V Maximum Power Dissipation...................................2500 mW DC VCC or GND Current ............................................500 mA Electrical Characteristics Over the Operating Range[3] DC Output Current, per Pin ......................–25 mA to +25 mA DC Input Voltage[1] .........................................–3.0V to +7.0V DC Program Voltage..................................................... 13.0V Static Discharge Voltage........................................... > 1100V (per MIL–STD–883, method 3015) Operating Range[2] Range Commercial Industrial Military Ambient Temperature 0°C to +70°C –40°C to +85°C –55°C to +125°C (Case) VCC 5V ±5% 5V ±10% 5V ±10% Parameter VOH VOL VIH VIL IIX IOZ IOS ICC1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Standby) ICC2 Power Supply Current[6] tR Recommended Input Rise Time tF Recommended Input Fall Time Capacitance[7] Parameter Description CIN Input Capacitance COUT Output Capacitance AC Test Loads and Waveforms[7] Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8 mA GND < VIN < VCC VO = VCC or GND VCC = Max., VOUT = 0.5V[4, 5] VI = VCC or GND (No Load) Commercial Military/Industrial VI = VCC Load) f = or GND (No 1.0 MHz[5, 6] Commercial Military/Industrial Min. 2.4 2.2 – 0.3 – 10 – 40 – 30 Max. Unit V 0.45 V VCC + 0.3 V 0.8 V +10 µA +40 µA –90 mA 125 mA 200 mA 135 mA 225 mA 100 ns 100 ns Test Conditions VIN = 2V, f = 1.0 MHz VOUT = 2.0V, f = 1.0 MHz Max. 10 10 Unit pF pF 5V OUTPUT R1 464Ω 5V OUTPUT R1 464 Ω 50 pF INCLUDING JIG AND SCOPE R2 250Ω (a) 5 pF R2 250Ω INCLUDING JIG AND SCOPE (b) 3.0V 10% GND < 6 ns ALL INPUT PULSES 90% 90% 10% < 6 ns Equivalent to: THÉVENIN EQUIVALENT (commercial/military) OUTPUT 163 Ω 1.75V Notes: 1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns. 2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 3. Typical values are for TA = 25°C and VCC = 5V. 4. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 5. Guaranteed but not 100% tested. 6. Measured with device programmed as a 16-bit counter in each LAB. This parameter is tested periodically by sampling production material. 7. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device. Document #: 38-03015 Rev. B Page 5 of 19 5 Page USE ULTRA37000™ FOR ALL NEW DESIGNS CY7C343 External Asynchronous Switching Characteristics Over Operating Range (continued)[7] Parameter tAOH Description Output Data Stable Time from Asynchronous Clock Input[5, 27] Com’l/Ind Mil 7C343-30 Min. Max. 15 15 7C343-35 Min. Max. Unit 15 ns 15 Internal Switching Characteristics Over Operating Range [7] 7C343-20 7C343-25 Parameter Description Min. Max. Min. Max. Unit tIN Dedicated Input Pad and Buffer Delay Com’l/Ind 4 5 ns Mil 4 5 tIO I/O Input Pad and Buffer Delay Com’l/Ind 4 5 ns Mil 4 5 tEXP Expander Array Delay Com’l/Ind Mil 10 12 ns 10 12 tLAD Logic Array Data Delay Com’l/Ind Mil 10 12 ns 10 12 tLAC Logic Array Control Delay Com’l/Ind Mil 8 10 ns 8 10 tOD Output Buffer and Pad Delay tZX Output Buffer Enable Delay[28] Com’l/Ind Mil Com’l/Ind Mil 4 5 ns 45 8 10 ns 8 10 tXZ Output Buffer Disable Delay Com’l/Ind Mil 8 10 ns 8 10 tRSU Register Set-Up Time Relative to Clock Signal Com’l/Ind 4 at Register Mil 4 6 ns 6 tRH Register Hold Time Relative to Clock Signal at Com’l/Ind 4 Register Mil 4 6 ns 6 tLATCH Flow-Through Latch Delay Com’l/Ind Mil 2 3 ns 23 tRD Register Delay Com’l/ Ind 1 1 ns Mil 1 1 tCOMB Transparent Mode Delay[29] Com’l/Ind 2 3 ns Mil 2 3 tCH Clock HIGH Time Com’l/Ind Mil 6 6 8 ns 8 tCL Clock LOW Time Com’l/Ind Mil 6 6 8 ns 8 tIC Asynchronous Clock Logic Delay Com’l/Ind Mil 12 14 ns 12 14 tICS Synchronous Clock Delay Com’l/Ind 2 2 ns Mil 2 2 Notes: 28. Sample tested only for an output change of 500 mV. 29. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation. Document #: 38-03015 Rev. *B Page 11 of 19 11 Page

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