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CXA3106AQ 데이터시트 PDF




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부품번호 CXA3106AQ 기능
기능 PLL IC for LCD Monitor/Projector
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CXA3106AQ 데이터시트, 핀배열, 회로
CXA3106AQ
PLL IC for LCD Monitor/Projector
Description
The CXA3106AQ is a PLL IC for LCD monitors/
projectors with built-in phase detector, charge pump,
VCO and counter.
The various internal settings are performed by
serial data via a 3-line bus.
Applicable LCD monitor/projector resolution are
NTSC, PAL, VGA, SVGA, XGA, and SXGA etc.
48 pin QFP (Plastic)
Features
Supply voltage: 5V ± 10% single power supply
Package: 48-pin QFP
Power consumption: 350mW
Sync input frequency: 10 to 100kHz
Clock output signal frequency: 10 to 160MHz
Clock delay: 1/16 to 20/16 CLK
Sync delay: 1/16 to 20/16 CLK
I/O level: TTL, PECL (complementary)
Low clock jitter
1/2 clock output
Pin Configuration (Top View)
Functions
Phase detector enable
UNLOCK output
Output TTL disable function
Power save function (2 steps)
Applications
CRT displays
LCD projectors
LCD monitors
Multi-media
36 35 34 33 32 31 30 29 28 27 26 25
IOGND 37
IOVCC 38
PLLVCC 39
PLLGND 40
VCOVCC 41
VCOGND 42
VCOHGND 43
IREF 44
RC2 45
RC1 46
IRGND 47
IRVCC 48
24 DSYNC
23 CLK
22 CLKN
21 CLK/2
20 CLK/2N
19 DGND
18 DVCC
17 UNLOCK
16 DIVOUT
15 SEROUT
14 CS
13 TLOAD
1 2 3 4 5 6 7 8 9 10 11 12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97812A03




CXA3106AQ pdf, 반도체, 판매, 대치품
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Symbol
IOVCC
IOGND
VCOH
VCOL
VCO
HOLD
SYNCH
SYNCL
SYNC
SENABLE
SCLK
SDATA
TLOAD
CS
SEROUT
DIVOUT
UNLOCK
DVCC
DGND
CLK/2N
CLK/2
CLKN
CLK
DSYNC
TTLGND
TTLVCC
IOGND
PECLVCC
CLK/2L
CLK/2H
CLKL
CLKH
DSYNCL
DSYNCH
VBB
PECLVCC
IOGND
IOVCC
PLLVCC
PLLGND
VCOVCC
VCOGND
VCOHGND
IREF
RC2
RC1
IRGND
IRVCC
Description
Digital power supply
Digital GND
External VCO input
External inverted VCO input
External VCO input
Phase detector disable signal input
Sync input
Inverted sync input
Sync input
Control signal (enable)
Control signal (clock)
Control signal (data)
Programmable counter test input
Chip select
Register read output
Programmable counter test output
Unlock signal output
Digital power supply
Digital GND
Inverted 1/2 clock output
1/2 clock output
Inverted clock output
Clock output
Delay sync signal output
TTL output GND
TTL output power supply
Digital GND
PECL output power supply
Inverted 1/2 clock output
1/2 clock output
Inverted clock output
Clock output
Delay sync signal output
Inverted delay sync signal output
PECL reference voltage
PECL output power supply
Digital GND
Digital power supply
PLL circuit analog power supply
PLL circuit analog GND
VCO circuit analog power supply
VCO circuit analog GND
VCO SUB analog GND
Charge pump current preparation
External pin for LPF
External pin for LPF
IREF analog GND
IREF analog power supply
–4–
CXA3106AQ
Reference voltage level
5V
0V
PECL
PECL
TTL
TTL
PECL
PECL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
5V
0V
TTL
TTL
TTL
TTL
TTL
0V
5V
0V
5V
PECL
PECL
PECL
PECL
PECL
PECL
PECLVCC – 1.3V
5V
0V
5V
5V
0V
5V
0V
0V
1.3V
1.7 to 4.4V
2.1V
0V
5V

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CXA3106AQ 전자부품, 판매, 대치품
CXA3106AQ
Pin Symbol I/O Reference
No. voltage level
5 VCO
I TTL
Equivalent circuit
6 HOLD
I TTL
9 SYNC
I TTL
10 SENABLE I TTL
IOVCC
5 10
6 11
9 12
13
IOGND
r/2
r
1.5V
2r
11 SCLK
I TTL
12 SDATA I TTL
13 TLOAD I TTL
Description
External VCO input.
Programmable counter test input
(controlled by a control register).
When using the VCO TTL input, open
the Pin 3 VCOH and Pin 4 VCOL
PECL inputs.
Phase detector disable signal.
Active high. When this pin is high, the
phase detector output is held. This pin
goes to high level when open.
(See the HOLD Timing Chart.)
Sync input.
When using the SYNC TTL input,
open the Pin 7 SYNCH and Pin 8
SYNCL PECL inputs.
The sync signal can be switched
between positive/negative polarity by
a control register.
Control signal (enable) for setting the
internal registers.
When SENABLE is low, registers can
be written; when high, registers can be
read.
(See the Control Register Table and
Control Timing Chart.)
Control signal (clock) for setting the
internal registers.
When SENABLE is low, SDATA is
loaded to the registers at the rising
edge of SCLK.
When SENABLE is high, the register
contents are output from SEROUT at
the falling edge of SCLK.
(See the Control Register Table and
Control Timing Chart.)
Control signal (data) for setting the
internal registers.
(See the Control Register Table and
Control Timing Chart.)
Programmable counter test input.
This pin is normally open status and
high. Register contents can be loaded
immediately to Programmable counter
by setting TLOAD low during the
programmable counter test mode.
–7–

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관련 데이터시트

부품번호상세설명 및 기능제조사
CXA3106AQ

PLL IC for LCD Monitor/Projector

Sony Corporation
Sony Corporation

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