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PDF CXA3197 Data sheet ( Hoja de datos )
| Número de pieza | CXA3197 | |
| Descripción | 10-bit 125MSPS D/A Converter | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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10-bit 125MSPS D/A Converter
CXA3197R
Description
The CXA3197R is a high-speed D/A converter
which can perform multiplexed input of two system
10-bit data.
This IC realizes a maximum conversion rate of
125MSPS. Multiplexed operation is possible by
inputing the 1/2 frequency-divided clock or by halving
the frequency of the clock internally with the clock
frequency divider circuit having the reset pin. The
data input is at TTL level, and the clock input and
reset input can select either TTL or PECL level
according to the application.
Features
• Maximum conversion rate:
During PECL operation: 125MSPS
During TTL operation: 100MSPS
• Resolution: 10 bits
• Low power consumption: 480mW (typ.)
• Data input level: TTL
• Clock, reset input level: TTL and PECL compatible
• 2:1 multiplexed input function
• 1/2 frequency-divided clock output possible by the
built-in clock frequency divider circuit
• Voltage output (50Ω load drive possible)
• Single power supply or ±dual power supply operation
• Reset signal polarity switching function
Pin Configuration
48 pin LQFP (Plastic)
LEAD TREATMENT: PALLADIUM PLATING
Structure
Bipolar silicon monolithic IC
Applications
• LCD
• DDS
• HDTV
• Communications (QPSK, QAM)
• Measuring devices
36 35 34 33 32 31 30 29 28 27 26 25
AGND2 37
VOCLP 38
R POLARITY 39
INV 40
PS 41
DVCC1 42
N.C. 43
DGND1 44
(MSB) DA9 45
DA8 46
DA7 47
DA6 48
24 RESETN/E
23 RESETP/E
22 RESET/T
21 CLKN/E
20 CLKP/E
19 CLK/T
18 DIV2OUT
17 DIV2IN
16 DB0 (LSB)
15 DB1
14 DB2
13 DB3
1 2 3 4 5 6 7 8 9 10 11 12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97639-PS
1 page  
CXA3197R
Pin Description and I/O Pin Equivalent Circuit
Pin No. Symbol I/O Typical voltage level
Equivalent circuit
Description
1 to 6
45 to 48
DA0 to DA9
I
TTL
7 to 16 DB0 to DB9 I
TTL
DVCC1
1 to 6
45 to 48
7 to 16
DGND1
Side A data input.
1.5V
Side B data input.
17 DIV2IN
I
TTL
DVCC1
17
DGND1
18 DIV2OUT O
TTL
19 CLK/T
DVCC1
I TTL
19
DGND1
1/2 frequency-divided
clock input.
Use this pin in MUX.1A
or MUX.2 mode.
1.5V Leave open for other
modes.
DVCC1
18
DGND1
1/2 frequency-divided
clock output.
The 1/2 frequency-
divided clock signal
(DIV2OUT) is output in
MUX.1A mode.
Set to high impedance
for other modes.
Clock input.
Use this pin when the
clock is input at TTL
level.
1.5V At this time, leave Pins
20 and 21 open.
–5–
5 Page 
CXA3197R
∗4 The current consumption in power saving mode does not include the VREF pin output current. When
grounding the VREF pin to the AGND2 level using external resistance, a voltage of 1.18 to 1.32V is
generated at the VREF pin even in power saving mode. Therefore, the current indicated by the following
equation flows from the AVCC2 pin to the VREF pin. This value must be added to obtain the actual current
consumption in power saving mode.
VREF pin voltage = IREFOUT
External resistance
AVCC2
BGR
VREF
34
In power saving mode:
VREF pin voltage
IREFOUT =
External resistance
AGND2
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXA3197.PDF ] | |
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