PDF CXA3205N Data sheet ( Hoja de datos )

Número de pieza	CXA3205N
Descripción	All Band TV Tuner IC with On-chip PLL
Fabricantes	Sony Corporation
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No Preview Available ! CXA3205N All Band TV Tuner IC with On-chip PLL Description The CXA3205N is a monolithic TV tuner IC which integrates local oscillator and mixer circuits for VHF band, local oscillator and mixer circuits for UHF band, an IF amplifier and a tuning PLL onto a single chip, enabling further miniaturization of the tuner. The PLL on this IC supports the I2C bus format. 30 pin SSOP (Plastic) Features • Low noise figure • Low power consumption (5 V, 58 mA typ.) • On-chip tuning PLL (I2C bus format) • Selection of frequency steps 31.25 kHz, 50 kHz and 62.5 kHz • On-chip 4-output band switch • IF balanced output Applications • TV tuners • VCR tuners • CATV tuners Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25 °C) • Supply voltage VCC1,VCC2 –0.3 to +5.5 V VCC3 –0.3 to +10.0 V • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 880 mW (when mounted on a substrate) Operating Conditions • Supply voltage VCC1, VCC2 VCC3 • Operating temperature Topr 4.75 to 5.30 4.75 to 9.45 –25 to +75 V V °C Note) Electrostatic discharge strength is weak, and care should be taken in handling this IC. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E97903-TE 1 page Pin Symbol No. 22 VCC2 23 GND2 24 IFOUT2 25 IFOUT1 26 LOCK 27 CPE 28 CPO CXA3205N Equivalent circuit — — 8 VCC1 15 15 24 25 Pin voltage (V) Description — PLL circuit power supply. — PLL circuit GND. 3.0 IF outputs. 3.0 VCC2 22 40k 26 5.0 (Lock) 0.2 (UNLock) LOCK detection. High when locked, Low when unlocked. VCC2 200 500 20k 22 28 27 NPN transistor connection for 0.6 varicap diode drive. Charge pump output. 2.0 Connect a loop filter. 29 REFOSC 29 60k 30p 30p Crystal connection for 4.3 reference oscillator. 30 VCC3 Power supply for external — supply. —5— 5 Page CXA3205N Description of PLL Block The PLL on this IC supports the I2C bus control format. The control pins are as shown in the table below. Symbol ADSW SCL SDA Description Address selection SCL input SDA I/O 1) Mode Setting Method The modes for each frequency step are set according to the MS pin voltage. Mode B-0 B-1 B-2 B-3 B-4 MS pin voltage 0 to 0.15 VCC OPEN 0.45 VCC to 0.55 VCC 0.65 VCC to 0.75 VCC 0.85 VCC to VCC Main divider 15 bit 14 bit 15 bit 15 bit 15 bit Reference divider 1024 512 640 512 512/ 640/ 1024 Reference frequency 3.90625 kHz 7.8125 kHz 6.25 kHz 7.8125 kHz 7.8125 kHz/ 6.25 kHz/ 3.90625 kHz ∗ Frequency step is for when X’tal OSC = 4 MHz. Frequency step∗ 31.25 kHz 62.5 kHz 50 kHz 62.5 kHz 62.5 kHz/ 50 kHz/ 31.25 kHz 2) Address Setting The responding address can be changed according to the ADSW pin voltage, so that multiple PLL can exist within one system. Address ADSW pin voltage 0 to 0.1 VCC OPEN or 0.2 VCC to 0.3 VCC 0.4 VCC to 0.6 VCC 0.9 VCC to VCC MA1 0 0 1 1 MA0 0 1 0 1 —11— 11 Page

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