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PDF CXA3268AR Data sheet ( Hoja de datos )
| Número de pieza | CXA3268AR | |
| Descripción | Driver/Timing Generator for Color LCD Panels | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXA3268AR
Driver/Timing Generator for Color LCD Panels
Description
The CXA3268AR is an IC designed to drive the color
LCD panels ACX300, ACX301, ACX302 and ACX703.
This IC greatly reduces the number of peripheral
circuits and parts by incorporating a RGB driver and
timing generator for video signals onto a single chip.
This chip has a built-in serial interface circuit and
electronic attenuators which allow various settings to
be performed by microcomputer control, etc.
72 pin LQFP (Plastic)
Features
• Color LCD panel ACX300, ACX301, ACX302 and
ACX703 driver
• Supports NTSC and PAL systems
• Supports 16:9 wide display (letter box and pulse
elimination display)
• Supports Y/color difference and RGB inputs
• Supports OSD input (digital input)
• Power saving function
• Serial interface circuit
• Electronic attenuators (D/A converter)
• Trap and LPF (f0, fc variable)
• COMMON and PSIG output circuits
• Sharpness function
• 2-point γ correction circuit
• R, G, B signal delay time adjustment circuit
• D/A output pin (0 to 3V, 8 level output)
• Output polarity inversion circuit
• Supports AC drive for LCD panel during no signal
Applications
Compact LCD monitors, etc.
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VCC1
6
V
VCC2
15
V
VCC3
15
V
VDD 5.5 V
• Analog input pin voltage
VINA (Pins 57, 58 and 59)
GND – 0.3 to VCC1 + 0.3 V
VINA (Pins 3, 69)
VCC1
V
VINA (Pin 30)
1.5 to VCC2 – 4
V
VINA (Pin 71)
0.9 Vp-p
VINA (Pins 70, 72)
0.8 Vp-p
• Digital input pin voltage
VIND (other than Pins 5, 10, 14, 15 and 16)
VSS – 0.3 to VDD + 0.3 V
VIND (Pins 5, 10)
VSS – 0.3 to +5.5 V
• Common input pin voltage
VINAD (Pins 14, 15 and 16)
GND, VSS – 0.3 to +5.5 V
• Operating temperature
Topr
–15 to +75 °C
• Storage temperature
Tstg –55 to +150 °C
• Allowable power dissipation
PD (Ta ≤ 25°C) 737
mW
Operating conditions
• Supply voltage
VCC1 – GND1 2.7 to 3.6
V
VCC2 – GND2 11.0 to 14.0
V
VCC3 – GND3 11.0 to 14.0
V
VDD – Vss
2.7 to 3.6
V
• Input voltage
SIG.C voltage
VSIG.C
5.0 to 6.5
V
RGB input signal voltage (Pins 70, 71 and 72)∗1
VRGB
0 to 0.7 (0.5 typ.) Vp-p
Y input signal voltage (Pin 71)∗2
VY 0 to 0.5 (0.35 typ.) Vp-p
R-Y input voltage (Pin 72)∗2
VR-Y
0 to 0.49 (0.245 typ.) Vp-p
B-Y input voltage (Pin 70)∗2
VB-Y
0 to 0.622 (0.311 typ.) Vp-p
∗1 During RGB input
∗2 During Y/color difference input
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99529B98-PS
1 page  
Analog Block Pin Description
Pin
No.
Symbol
Pin
voltage
2 FIL OUT
2.15V
Equivalent circuit
VCC1
2
23k
200
GND1
3 SYNC IN
1.1V
4 SYNC OUT —
6 DA OUT
—
VCC1
200
3
GND1
VCC1
4
GND1
VCC1
6
GND1
50
50
7 REF
—
VCC1
7
GND1
51k
–5–
CXA3268AR
Description
Amplifies and outputs the sync
portion of the video signal input
to FIL IN (Pin 69).
Sync separation circuit input.
Inputs the FIL OUT (Pin 2)
output signal via a capacitor.
Sync separation output.
Positive polarity output in open
collector format.
DA output.
Outputs the serial data
converted to DC voltage. The
current driving capacity is
±1.0mA (max.).
REF output.
Outputs the serial data
converted to DC voltage. The
current driving capacity (sink)
is ±1.5mA (max.).
5 Page 
CXA3268AR
Setting Conditions for Measuring Electrical Characteristics
Use the Electrical Characteristics Measurement Circuit on page 22 when measuring electrical characteristics.
For measurement, the digital block must be initialized and power saving must be canceled by performing
Settings 1 and 2 below. In addition, the serial data must be set to the initial settings shown in the table below.
Setting 1. Horizontal AFC adjustment
Input a signal and adjust the VCO using V22 so that WL and WH of the TP24 output waveform are the same.
Setting 2. Canceling power saving mode
The power-on default is power saving mode, so clear (set all "0") serial data PS0, PS1, PS2, PS4 and SYNC GEN.
Horizontal sync
signal
RPD (Pin 24)
WS
WS
WL WH
WL WH
Fig. 1. Horizontal AFC adjustment
WL = WH
Serial data initial settings
MSB
ADDRESS
LSB MSB
DATA
LSB
D15 D14 D13 D12 D11 D10
000000
000000
000000
000000
000001
000001
000001
000001
000010
000010
000010
000010
D9
0
0
1
1
0
0
1
1
0
0
1
1
0000110
0000110
0000111
0000111
0001000
0010000
0010000
0010001
0010001
0010010
D8 D7 D6 D5 D4 D3 D2 D1 D0
0
USER-BRIGHT
(01000110/LSB)
1 SUB-BRIGHT R (10001010/LSB)
0 SUB-BRIGHT B (10001010/LSB)
1
CONTRAST
(00111111/LSB)
0 SUB-CONTRAST R (10011111/LSB)
1 SUB-CONTRAST B (10011111/LSB)
0 γ-2 (11111111/LSB)
1 γ-1 (11111111/LSB)
00
PSIG-BRIGHT
(1011111/LSB)
1
COM-DC
(10000000/LSB)
0
COLOR
(00000000/LSB)
1
HUE
(10000000/LSB)
0
0
WHITE-LIMITER
(00/LSB)
BLACK-LIMITER (11111/LSB)
1 FILTER (00/LSB) REF (000/LSB)
LPF (000/LSB)
0 PICTURE-GAIN (00000/LSB)
0
PICTURE-F0
(00/LSB)
1 0 0 0 0 MODE (1) DA (000/LSB)
00
0
SYNC GEN PS 4
(0) (0)
0
PS 2 PS 1 PS 0
(0) (0) (0)
0 SLSYP (1) SLEXVD (0) SLDWN (0) SLRGT (0) SLSH2 (1) SLSH1 (1) SLWD (0) SLPL (0)
1 0 SLFL (0) SLFR (0) SL4096 (0) SLCLP2 (0) SLCLP1 (0) SLVDP (0) SLHDP (0)
00
0 SLTST4 (0) SLTST3 (0) SLSH0 (1) SLTST2 (0) SLTST1 (0) SLTST0 (0)
10 0 0
H-POSITION (10000)
00 0 0
HD-POSITION (00000)
Note) If there is the possibility that data may be set at other than the above-noted addresses, set these data to "0".
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXA3268AR.PDF ] | |
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