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PDF CXA7000R Data sheet ( Hoja de datos )
| Número de pieza | CXA7000R | |
| Descripción | LCD Driver | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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LCD Driver
Description
The CXA7000R is a driver IC developed for use
with Sony polycrystalline silicon TFT LCD panels. It
supports 10-bit digital input, and the input data is
analog demultiplexed into 6 phases and output. The
CXA7000R can directly drive an LCD panel, and the
VCOM setting circuit and precharge pulse waveform
generator are also on-chip.
Features
• Supports 10-bit input
• Supports signals up to XGA
• Low output deviation by on-chip output offset cancel circuit
• On-chip timing generator with ECL
• VCOM voltage generation circuit
• Precharge pulse waveform generation circuit
Applications
LCD projectors and other video equipment
Absolute Maximum Ratings (VSS = 0V)
• Supply voltage
VCC 16 V
VDD 5.5 V
• Operating temperature
Topr –20 to +70 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation PD
1250 mW
Recommended Operating Conditions
• Supply voltage
VCC 15.0 to 15.5
VDD 4.75 to 5.25
• Operating temperature
Topr –20 to +70
V
V
°C
CXA7000R
64 pin LQFP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01821A22
1 page  
CXA7000R
Pin
No.
Symbol
37 PRG_LV
38 SID_LV
I/O
Standard
voltage level
VDD
I 1.0 to 5.0V
37
38
GND
Equivalent circuit
29µ
50k
50k
Description
VCC
Precharge level setting.
Adjusts the SID_OUT and
SID_OUTX output potential.
PRG_LV is reflected when the
PRG input pin (Pin 60) is high,
and SID_LV is reflected when
PRG is low.
39 PRG
VDD
I
High: ≥2.0V
Low: ≤0.8V
39
GND
VDD
100k
10k
VCC
50µ
70µ 10µ
44 VREF_I
I
3.2V
44
GND
VDD
1k
280µ
33.3k
2k
45 VREF_O O
3.2V
46 F/H_CNT
High: ≥2.0V
I Low: ≤0.8V
Open: Low
47 DIRC
I
High: ≥2.0V
Low: ≤0.8V
20µ
GND
20k
12.4k
45
VDD
46
GND
50k
192
200k
VDD
50k
192
47
GND
Timing pulse input for switching
the Pin 36 output levels.
(See PRG_LV (Pin 37) and
SID_LV (Pin 38).)
Internal D/A converter reference
voltage input.
Normally connect directly to
VREF_O.
Reference voltage output.
Normally connect directly to
VREF_I, and connect to GND
through a 0.5 to 1.0µF capacitor.
SH_OUT output timing selection.
High: SH_OUT1 to SH_OUT3
and SH_OUT4 to SH_OUT6
are output at different timing.
Low: SH_OUT1 to SH_OUT6
are output at the same timing.
Scan direction setting.
High: output as a time series in
ascending order of output pin
symbol (in order from SH_OUT1
to SH_OUT6)
Low: output in descending order
–5–
5 Page 
CXA7000R
Description of Operation
The flow of internal operations is described below.
The digital signals input to D_IN0 to D_IN9 are internally D/A converted into approximately 1.5V (at VREF_I:
3.2V) analog signals. After that, the signal that has been demultiplexed into 6 phases is amplified by a factor of
three times, inverted at the signal center potential according to FRP, and output.
The output level relative to the digital input changes according to the following settings.
A: SIG_OFST voltage
B: VREF_I voltage
C: SIG.C voltage
VCC
B
1023
512
0
Digital IN
A
Signal Center
A
C
B
SH_OUT
GND
1. Digital input block
The CXA7000R can be set to master/slave mode, single mode and left/light inversion. This makes it possible to
support various systems.
In master/slave mode, the even and odd data is internally selected respectively and input to the D/A converter.
2. D/A converter block
The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input
from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a
maximum 1.5Vp-p with respect to input data of 000h to 3FFh.
3. Sample-and-hold (S/H) block
The D/A converter outputs are input to the sample-and-hold blocks, respectively. The signals are converted from
time series signals into 6-phase cyclic parallel signals by the sample-and-hold group which is appropriately
controlled by the internal timing generator. For forward scan, the signals are output in the ascending order of
SH_OUT1, SH_OUT2, SH_OUT3 ... SH_OUT6. For reverse scan, this order is inverted and the signals are
output in descending order. Connect the signals to the LCD panel according to the order used. The timing of
each sample-and-hold pulse is shown on the following pages. These pulses are not output and are used only
inside the IC.
– 11 –
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet CXA7000R.PDF ] | |
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