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PDF CXD2588R Data sheet ( Hoja de datos )
| Número de pieza | CXD2588R | |
| Descripción | CD Digital Signal Processor with Built-in Digital Servo and DAC | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD2588Q/R
CD Digital Signal Processor with Built-in Digital Servo and DAC
For the availability of this product, please contact the sales office.
Description
The CXD2588Q/R is a digital signal processor LSI
for CD players. This LSI incorporates a digital servo,
digital filter, zero detection circuit, 1-bit DAC and
analog low-pass filter on a single chip.
CXD2588Q
100 pin QFP (Plastic)
CXD2588R
100 pin LQFP (Plastic)
Features
Digital Signal Processor (DSP) Block
• Playback mode which supports CAV (Constant
Angular Velocity)
• Frame jitter free
• 0.5× to 4× continuous playback possible
• Allows relative rotational velocity readout
• Supports spindle external control
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports normal-speed, 4× speed playback
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Digital audio interface outputs
• Digital level meter, peak meter
• CD TEXT data demodulation
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
Digital Filter, DAC and Analog Low-Pass Filter Blocks
• DBB (digital bass boost) function
• Double-speed playback supported
• Digital de-emphasis
• Digital attenuation
• Zero detection function
• 8Fs oversampling digital filter
• S/N: 100dB or more (master clock: 384Fs, typ.)
• Logical value: 109dB
• THD + N: 0.007% or less (master clock: 384Fs, typ.)
• Rejection band attenuation: –60dB or less
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage
VDD
–0.3 to +7.0 V
• Input voltage
VI
–0.3 to +7.0 V
(VSS – 0.3V to VDD + 0.3)
• Output voltage
VO
–0.3 to +7.0 V
• Storage temperature Tstg
–40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Recommended Operating Conditions
• Supply voltage
VDDNote)
+2.7 to +5.5 V
• Operating temperature Topr
–20 to +75 °C
Note) The VDD for the CXD2588Q/R varies according
to the playback speed selection.
Playback
speed
4×
1×
1×
VDD [V]
CD-DSP block
DAC block
4.75 to 5.25
3.0 to 5.5
4.5 to 5.5
2.7 to 5.5
2.7 to 5.5
I/O Capacitance
• Input pin
• Output pin
• I/O pin
CI
CO
CI/O
11 (Max.)
11 (Max.)
11 (Max.)
pF
pF
pF
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97519-PS
1 page  
CXD2588Q/R
Pin Description
Pin No.
CXD CXD
2588R 2588Q
Symbol
1 3 SQSO
2 4 SQCK
3 5 SBSO
4 6 EXCK
5 7 XRST
6 8 SYSM
7 9 DATA
8 10 XLAT
9 11 CLOK
10 12 SENS
11 13 SCLK
12 14 PWMI
13 15 VDD
14 16 VDD
15 17 ATSK
16 18 SPOA
17 19 SPOB
18 20 XLON
19 21 WFCK
20 22 XUGF
21 23 XPCK
22 24 GFS
23 25 C2PO
24 26 SCOR
25 27 C4M
26 28 WDCK
27 29 COUT
28 30 MIRR
29 31 DFCT
30 32 FOK
31 33 LOCK
32 34 MDP
33 35 SSTP
34 36 FSTO
I/O
Output
values
Description
O
1, 0
Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data
output.
I SQSO readout clock input.
O 1, 0 Sub Q P to W serial output.
I SBSO readout clock input.
I System reset. Reset when low.
I Mute input. Muted when high.
I Serial data input from CPU.
I Latch input from CPU. Serial data is latched at the falling edge.
I Serial data transfer clock input from CPU.
O 1, 0 SENS output to CPU.
I SENS serial data readout clock input.
I Spindle motor external control input.
— — Digital power supply.
— — Digital power supply.
I/O 1, 0 Anti-shock input/output.
I Microcomputer extension interface (input A)
I Microcomputer extension interface (input B)
O 1, 0 Microcomputer extension interface (output)
O 1, 0 WFCK output.
O 1, 0 XUGF output. MINT1 or RFCK is output by switching with the command.
O 1, 0 XPCK output. MNT0 is output by switching with the command.
O 1, 0 GFS output. MNT3 or XROF is output by switching with the command.
O 1, 0 C2PO output. GTOP is output by switching with the command.
O 1, 0 Outputs a high signal when either subcode sync S0 or S1 is detected.
O 1, 0 4.2336MHz output. In CAV-W mode, 1/4 frequency division output for VCKI.
O 1, 0 Word clock output. f = 2Fs.
I/O 1, 0 Track count signal input/output.
I/O 1, 0 Mirror signal input/output.
I/O 1, 0 Defect signal input/output.
I/O 1, 0 Focus OK signal input/output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a
I/O 1, 0 high signal. If GFS is low eight consecutive samples, this pin
outputs low. Or input when LKIN = 1.
O 1, Z, 0 Spindle motor servo control output.
I Disc innermost track detection signal input.
O 1, 0 2/3 frequency division output for XTAI pin.
–5–
5 Page 
CXD2588Q/R
(2) CLOK, DATA, XLAT, COUT, SQCK, and EXCK pins
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min.
Clock frequency
fCK
Clock pulse width
tWCK
750
Setup time
tSU 300
Hold time
tH 300
Delay time
tD 300
Latch pulse width
tWL
750
EXCK, SQCK frequency fT
EXCK, SQCK pulse width fWT
750Note)
Typ.
Max. Unit
0.65 MHz
ns
ns
ns
ns
ns
0.65Note) MHz
ns
CLOK
1/fCK
tWCK
tWCK
DATA
XLAT
EXCK
SQCK
SBSO
SQSO
tSU tH
tWT tWT
1/fT
tSU tH
tD tWL
Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum
operating frequency is 300kHz and its minimum pulse width is 1.5µs.
(3) BCKI, LRCKI and PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
BCK pulse width
DATAL, R setup time
DATAL, R hold time
LRCK setup time
Symbol Conditions
tW
tSU
tH
tSU
Min.
94
18
18
18
Typ.
Max.
Unit
ns
ns
ns
ns
tW(BCKI) tW(BCKI)
BCKI
VDD/2
VDD/2
tSU tH
(PCMDI) (PCMDI)
PCMDI
tSU
(LRCKI)
LRCKI
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD2588R.PDF ] | |
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