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PDF CXD2597Q Data sheet ( Hoja de datos )
| Número de pieza | CXD2597Q | |
| Descripción | CD Digital Signal Processor with Built-in Digital Servo and DAC | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD2597Q
CD Digital Signal Processor with Built-in Digital Servo and DAC
For the availability of this product, please contact the sales office.
Description
The CXD2597Q is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter, zero detection circuit, 1-bit DAC and
analog low-pass filter on a single chip.
80 pin QFP (Plastic)
Features
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular
Velocity)
• Frame jitter free
• 0.5× to 4× continuous playback possible
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports normal-speed to 4× speed playback
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Digital audio interface outputs
• Digital level meter, peak meter
• CD TEXT data demodulation
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
Digital Filter, DAC and Analog Low-Pass Filter Blocks
• DBB (digital bass boost) function
• Double-speed playback supported
• Digital de-emphasis
• Digital attenuation
• Zero detection function
• 8Fs oversampling digital filter
• S/N: 100dB or more (master clock: 384Fs, typ.)
Logical value: 109dB
• THD + N: 0.007% or less (master clock: 384Fs, typ.)
• Rejection band attenuation: –60dB or less
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage
VDD
–0.3 to +7.0 V
• Input voltage
VI
–0.3 to +7.0 V
(VSS – 0.3V to VDD + 0.3)
• Output voltage
VO
–0.3 to +7.0 V
• Storage temperature Tstg
–40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Note) AVDD includes XVDD and AVSS includes XVSS.
Recommended Operating Conditions
• Supply voltage
VDD
+2.7 to +5.5 V
• Operating temperature Topr
–20 to +75 °C
Note) The VDD for the CXD2597Q varies according to
the playback speed selection.
Playback
speed
4×
2×
1×
VDD [V]
CD-DSP block
DAC block
4.75 to 5.25
3.0 to 5.5
4.5 to 5.5
2.7 to 5.5
2.7 to 5.5
I/O Capacitance
• Input capacitance CI
• Output capacitance CO
• I/O capacitance CI/O
11 (Max.)
11 (Max.)
11 (Max.)
pF
pF
pF
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97Z35-PS
1 page  
CXD2597Q
Pin
No.
Symbol
I/O
Description
36 TES1
I
Test pin. Normally, GND.
37 XTSL
I
Crystal selection input. Low when the crystal is 16.9344MHz; high when the
crystal is 33.8688MHz.
38 VC
I
Center voltage input.
39 FE
I
Focus error signal input.
40 SE
I
Sled error signal input.
41 TE
I
Tracking error signal input.
42 RFDC
I
RF signal input.
43 AVSS0 — — Analog GND.
44 IGEN
I
Operational amplifier constant current input.
45 AVDD0 — — Analog power supply.
46 ASYO O 1, 0 EFM full-swing output. (low = Vss, high = VDD)
47 ASYI
I
Asymmetry comparator voltage input.
48 BIAS
I
Asymmetry circuit constant current input.
49 RFAC
I
EFM signal input.
50 AVSS3 — — Analog GND.
51 CLTV
I
Multiplier VCO1 control voltage input.
52 FILO
O Analog Master PLL filter output. (slave = digital PLL)
53 FILI
I
Master PLL filter input.
54 PCO
O 1, Z, 0 Master PLL charge pump output.
55 AVDD3 — — Analog power supply.
56 VCTL
I
Wide-band EFM PLL VCO2 control voltage input.
57 VPCO O 1, Z, 0 Wide-band EFM PLL charge pump output.
58 VSS
— — Digital GND.
59 VDD
— — Digital power supply.
60 DOUT O 1, 0 Digital Out output.
61 LRCK
O 1, 0 D/A interface. LR clock output f = Fs.
62 PCMD O 1, 0 D/A interface. Serial data output. (two's complement, MSB first)
63 BCK
O 1, 0 D/A interface. Bit clock output.
64 EMPH
O
1, 0
Outputs a high signal when the playback disc has emphasis, and a low
signal when there is no emphasis.
65 XVDD
— — Master clock power supply.
66 XTAI
I
Crystal oscillation circuit input. Master clock is externally input from this pin.
67 XTAO O
Crystal oscillation circuit output.
68 XVSS
— — Master clock GND.
69 AVDD1 — — Analog power supply.
70 AOUT1 O
L ch analog output.
71 AIN1
I
L ch operational amplifier input.
–5–
5 Page 
CXD2597Q
1-bit DAC and LPF Block Analog Characteristics
Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)
Item Symbol
Conditions
Total harmonic
distortion
THD
1kHz, 0dB data
Signal-to-noise
ratio
S/N
1kHz, 0dB data
(Using A-weighting filter)
Crystal
384Fs
768Fs
384Fs
768Fs
Min. Typ. Max. Unit
0.0050 0.0070
0.0045 0.0065
%
96 100
96 100
dB
Fs = 44.1kHz in all cases.
The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.
AOUT1 (2)
AIN1 (2)
LOUT1 (2)
12k
12k
150p
680p
12k
SHIBASOKU (AM51A)
22µ
100k
Audio Analyzer
LPF external circuit diagram
768Fs/384Fs
DATA
TEST DISC
Rch
RF
CXD2597Q
Lch
A
Audio Analyzer
B
Block diagram of analog characteristics measurement
(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit Applicable pins
Output voltage
VOUT
1.12
Vrms
∗1
Load resistance RL 8
kΩ ∗1
∗ Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB.
Applicable pins
∗1 LOUT1, LOUT2
– 11 –
11 Page | ||
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| PDF Descargar | [ Datasheet CXD2597Q.PDF ] | |
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