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PDF CXD3009Q Data sheet ( Hoja de datos )
| Número de pieza | CXD3009Q | |
| Descripción | CD Digital Signal Processor | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CD Digital Signal Processor
CXD3009Q
Description
The CXD3009Q is a digital signal processor LSI for
CD players and is equipped with built-in digital
filters, zero detection circuit, 1-bit DAC, and analog
low-pass filter on a single chip.
80 pin QFP (Plastic)
Features
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV
(Constant Angular Velocity)
– Frame jitter-free
– Allows 0.5 to double-speed continuous playback
– Allows relative rotational velocity readout
– Supports external spindle control
• Wide capture range playback mode
– Spindle rotational velocity following method
– Supports normal-speed and double-speed playback
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry compensation circuit
• Serial bus-based CPU interface
• Error correction monitor signals, etc. are output
from a new CPU interface.
• Servo auto sequencer
• Digital audio interface output
• Digital peak meter
• CD-TEXT data demodulation
Digital Filter, DAC, Analog Low-Pass Filter Block
• DBB (Digital Bass Boost)
• Supports double-speed playback
• Digital de-emphasis
• Digital attenuation function
• Zero detection function
• 8Fs oversampling digital filter
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD
–0.3 to +4.6
V
• Input voltage VI
–0.3 to +4.6
V
(Vss – 0.3V to VDD + 0.3V)
• Output voltage VO
–0.3 to +4.6
V
• Storage temperature
Tstg –40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3
V
VDD – AVDD –0.3 to +0.3
V
Note) AVDD includes XVDD, and AVSS includes XVSS.
Recommended Operating Conditions
• Supply voltage VDD
2.5 to 3.6
• Operating temperature
Topr
–20 to +75
V
°C
Input/Output Capacitances
• Input capacitance CI
12 (max.)
• Output capacitance CO
12 (max.)
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
pF
pF
Applications
CD players
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97322B01-PS
1 page  
CXD3009Q
Pin
No.
Symbol
I/O
Description
36 BIAS
I
Constant current input of the asymmetry circuit.
37 ASYI
I
Asymmetry comparator voltage input.
38 ASYO
O 1, 0 EFM full-swing output (low = VSS, high = VDD).
39 LRCK
O 1, 0 D/A interface. LR clock output f = Fs.
40 LRCKI
I
LR clock input.
41 PCMD O 1, 0 D/A interface. Serial data output (two's complement, MSB first).
42 PCMDI I
D/A interface. Serial data input (two's complement, MSB first).
43 BCK
O 1, 0 D/A interface. Bit clock output.
44 BCKI
I
D/A interface. Bit clock input.
45 VSS
— — GND
46 VDD
47 XUGF
— — Power supply (+3V).
O 1, 0 XUGF output. Switched to MNT1 or RFCK output by a command.
48 XPCK
O 1, 0 XPLCK output. Switched to MNT0 output by a command.
49 GFS
O 1, 0 GFS output. Switched to MNT3 or XRAOF output by a command.
50 C2PO
O 1, 0 C2PO output. Switched to GTOP output by a command.
51 XTSL
I
Crystal selector input. Low: 16.9344MHz; high: 33.8688MHz.
52 C4M
O 1, 0 4.2336MHz output. 1/4 frequency-divided VCKI output in CAV-W mode.
53 DOUT O 1, 0 Digital Out output.
54 EMPH
Outputs a high signal when the playback disc has emphasis, and a low
O 1, 0 signal when there is no emphasis.
55 EMPHI I
Inputs a high signal when de-emphasis is on, and a low signal when
de-emphasis is off.
56 WFCK O 1, 0 WFCK output.
57 SCOR O 1, 0 Outputs a high signal when either subcode sync S0 or S1 is detected.
58 SBSO O 1, 0 Sub P to W serial output.
59 EXCK
I
SBSO readout clock input.
60 VSS
— — GND
61 VDD
62 SYSM
— — Power supply (+3V).
I Mute input. Active when high.
63 AVSS
64 AVDD
— — Analog GND.
— — Analog power supply (+3V).
65 AOUT1 O
Left-channel analog output.
66 AIN1
I
Left-channel operational amplifier input.
67 LOUT1 O
Left-channel LINE output.
68 AVSS
69 XVDD
— — Analog GND.
Power supply for master clock.
70 XTAI
I
Crystal oscillation circuit input. Input the external master clock via this pin.
71 XTAO O
Crystal oscillation circuit output.
–5–
5 Page 
CXD3009Q
(VDD = AVDD = 3.3V, VSS = AVSS = 0V, Topr = – 20 to +75°C)
Item Symbol Min. Typ. Max. Unit Applicable pins
Output voltage
VOUT
0.70∗
Vrms
∗1
Load resistance
RL 20
kΩ ∗1
∗ Measured using the circuits on the previous page when a sine wave of 1kHz and 0dB is
output.
Applicable pins
∗1 LOUT1, LOUT2
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD3009Q.PDF ] | |
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